Three ‐ component Seismic Data Acquisition System Base on STM32 and ADS1285

: In the three-component seismic VSP seismic data acquisition, high-resolution and low-power seismic wave acquisition is an important research content of seismic exploration methods. In view of the problems of insufficient resolution and signal attenuation of existing geophones, which lead to distortion of seismic signals collected in complex strata. A digital downhole digital three-component detector based on ADS1285 is proposed. The design uses STM32F405 as the microcontroller, ADM2582E as the RS485 transmission chip, and uses the PPP communication protocol to achieve high-speed communication with the host computer. Experimental results show that the dynamic range of the data acquisition system based on ADS1285 is 135dB, and the average analog-to-digital conversion equivalent noise level is below 0.5μV, which can effectively improve the acquisition accuracy of field seismic exploration.


Introduction
The vertical seismic profile is a seismic exploration technique used to determine the subsurface rock structure and the distribution of oil and gas resources.This method involves the placement of seismic sensors in a borehole to record the velocity and amplitude of seismic waves generated by seismic instruments as they travel through the earth, providing valuable insights into subsurface rock structures [1].Seismic detectors, designed to convert seismic signals into electrical signals, are critical components in VSP surveys, enabling indepth investigations of subsurface structures.
In comparison to single-component seismic detectors, three-component seismic detectors offer a wealth of seismic wave data.Single-component detectors typically record vibrational data in only one direction (usually the X-axis) and are limited in their ability to accurately depict subsurface faults.As a result, they can provide only basic fault information during data processing [2].Three-component seismic detectors, on the other hand, can capture seismic wave data from three directions: X, Y, and Z.This threefold increase in data acquisition, compared to single-component detectors, significantly enhances the amount of information obtained, leading to improved accuracy in structural interpretation and inversion modeling [3].
In the realm of VSP seismic data acquisition systems, there are several notable options available globally, such as OYO GeoSpace's HDSeis borehole seismic instrument, Baker Atlas's Geochain VSP logging instrument, CGG's SST-500, and the JDB-30 borehole seismic multi-wave imaging acquisition system manufactured by China's Xi'an Instrument Factory.It's important to note that earlier VSP exploration systems utilized analog-to-digital converters with limited bit depth (ranging from 16 to 24 bits) [4].In cases where a 24-bit converter was employed, the practical effective resolution was reduced to 21 bits due to technical constraints [5].Such systems were unable to meet the demands of complex stratigraphic investigations.
This article presents a novel three-component seismic data acquisition system designed to enhance traditional VSP detectors.The system is based on STM32 and ADS1285 components, with particular emphasis on noise reduction, data precision, and signal resolution.Performance metrics for the designed system are thoroughly evaluated with the objective of advancing VSP technology for intricate stratigraphic investigations.

Design of the Overall System
The overall framework of three-component VSP acquisition is illustrated in Figure .1.The system consists of the ADS1285 analog to digital conversion module, RS485 data transmission module, MCU control module, and power supply module [6].
Among them, the analog-to-digital conversion module utilizes a 32-bit ADS1285 chip with a sampling rate of up to 4ksps.This module satisfies the requirements for high resolution, high signal-to-noise ratio, and low noise, making it suitable for micro-seismic signal acquisition.Additionally, it is compatible with various types of geophones such as moving coil geophones and digital MEMS geophones.The ADC analog-to-digital converter transforms analog seismic wave signals into digital signals that are subsequently processed, stored, and transmitted by other circuits.The power module employs a regulated power chip to provide stable and reliable power supply for the system.For data transmission to the host computer, the RS485 transmission module incorporates the ADM2582E chip [7].
The key design aspects of this system consist of two parts: overall circuit design with enhanced anti-interference capability including dynamic range configuration and low noise capability; MCU program design and implementation encompassing three-channel SPI configuration, three-channel time synchronization, and seismic data reading [8].

Front-end Acquisition Circuit
In order to enhance signal quality, the input signal is adjusted to effectively filter out high-frequency common mode interference in the lines and differential mode noise between the lines [8].The input signal is limited by overcurrent and overvoltage protection circuits before being fed into the differential input of the ADS1285.A current loop formed by R77 and R78 in the circuit enables obtaining a differential voltage signal.To eliminate high-frequency common-mode interfering noise within the circuit, a low-pass filter consisting of resistors R74, R73, capacitors C62, and C63 is employed.Additionally, resistors R74, R75 along with capacitor C3 form a differential mode filter.Notably, the capacitance value of capacitor C3 exceeds that of C62 and C63 by more than 10 times to effectively address common mode error caused by their mismatching.Schottky diodes D1, D2, D3, and D4 are incorporated into the circuit for limiting input signals and safeguarding against potential damage to the ADS1285 chip resulting from excessively high or low input signals.Furthermore, OPA391 serves as a voltage follower in  to provide a 2.5V DC offset for collecting negative signals from acquisition inputs [9].The front-end processing circuitry of ADS1285 is illustrated in Figure.

ADS1285 Acquisition Circuit Design
The seismic data acquisition signal spans multiple orders of magnitude, and for the purpose of low noise, high precision, and a large dynamic range, this design selects the Texas Instruments ADS1285 chip as the core ADC device.
The ADS1285 is an ADC specifically designed by Texas Instruments for seismic detection with a 32-bit resolution, 4kSPS sampling rate, and 2 channels.The selection of this chip takes into consideration the following factors: (1) The dual-channel input capability of ADS1285 enables both data acquisition and instrument self-test functions in underground mines.(3) With its digital filter feature, small signals can be processed using flexible combinations of FIR+IIR+Sinc filters with output rates ranging from 250 to 4kSPS.
Taking X signal acquisition as an example, the first channel serves as the input for seismic signals while the second channel is used for standard sine signal input to facilitate underground self-testing.The AVDD voltage for analog components is set at 5V while DVDD voltage for digital components uses 3.3V; additionally, a filter capacitor is added to eliminate power ripple effects.Conventional SPI communication mode is employed for interface purposes.
When operating, the active crystal oscillator has a frequency of 8.192MHz, the reference voltage provided by REF6421 is   4.096, and the minimum resolution in terms of removing the sign bit according to theoretical calculations is 4.096/2 0.0019 , which satisfies the requirements for high-precision seismic data acquisition.The data acquisition circuit of ADS1285 is illustrated in Figure.

Design of multiple analog-to-digital conversion parallel acquisition circuits
The three-component ADS1285 is connected to the STM32F405 pin, as illustrated in Figure .4. This demonstrates the connection of the ADS1285.The DRDY control output of each ADS1285 can be utilized.Three SPI control lines, namely CS, SCLK, MOSI and MISO, are employed for controlling parallel data transmission simultaneously across all three channels.To achieve high-performance operation mode, the CLK pin is linked with an 8.192MHz crystal oscillator.PWDN, RESET and SYNC are interconnected to enable simultaneous synchronization control of all three ADS1285 channels.

RS485 Transmission Circuit Design
he circuit design is illustrated in Figure 5.In this particular design, the ADM2582E serves as the RS485 transmission chip, functioning as an isolated RS-485/RS-422 transceiver that can be configured for either half-duplex or full-duplex mode of operation.The ADM2582E incorporates an isolated DC/DC converter and its RS-485 input/output pin offers ±15 kV ESD protection for transmission rates up to 16Mbps.In this design, RE and DE are connected to the PC13 pin on the master MCU to control the transmit and receive status of the ADM2582E.The main control MCU connects the RXD and TXD pins on the ADM2582E chip through USART6 to control the transmission and reception of RS485 [10].This design adopts half-duplex mode by connecting A and Y pins as A signal line, while B and Z pins serve as B signal line.Simultaneously, both power pins are linked to input terminal and ground signal, with 0.1uf and 100uf capacitors employed for decoupling and filtering purposes in order to ensure input power stability.
To prevent exceeding effective potential levels, a Schott diode is incorporated at the input for clamp protection.Additionally, a 120Ω resistor is connected to achieve impedance matching with respect to RS485 differential output; thereby effectively absorbing high-frequency reflections originating from transmission cables.

Main Control Design
The main control chip utilized in this design is the STM32F405RGT6, operating at a voltage of 3.3V and a clock frequency of 168MHz.It supports three-channel SPI, threechannel IIC, and multi-channel USART communication modes to meet the required design specifications.Please refer to Figure 6 for the schematic diagram of the main control design.The STM32F405RGT6 is connected in parallel with ADS1285 through three-channel SPI, while RS485 module is connected to serial port USART6 for data transmission at a baud rate of 230400.Serial port USART2 is separately exported and used for debugging purposes with TTL level set at a baud rate of 115200.PA4 serves as a DAC output waveform for instrument self-test, whereas PB1 connects to an indicator light that signifies the operational status of the instrument.to achieve high-performance acquisition mode.The configuration information is then written synchronously into the ADCs of the three components.

Main program design
The main program software design is based on the open source FreeRTOS, which is widely used in the development of various types of microcontrollers due to its portability, task scheduling and easy tailoring.The overall framework of the software is shown in Figure 8  The main functions of the software are as follows: Initialization tasks: Mainly complete the initialization functions of system clock, peripherals, and GPIO.
Interrupt tasks: Complete interrupts from the serial port and timer, complete data reception and transmission, and control of low-power mode.
Data collection task: Control ADS1285 data collection through three-way SPI communication.
Data sending task: control RS485 through the serial port and use PPP protocol to send data to the host computer.
Run detection tasks: Monitor the running status of each task, and place the task in a stuck state.First, the system completes the initialization of each peripheral and GPIO, and controls the RS485 module through the serial port to wait for the host computer to send a collection interrupt command.After receiving the external collection command, the ADS1285 starts to collect data, and the collected data is packaged and uploaded through the PPP protocol, and the collected data is uploaded through the RS485 module Send to host computer.

Data Collection Software Design
ADS1285 uses continuous data reading to collect seismic data as shown in Figure 9. First, by disabling external interrupt control, it is to avoid interrupts during data reading.Before the synchronization gate signal is generated, in order to delay the host failure, command distribution, and command transmission delay from the host computer to the geophone, the pre-acquisition and pre-read operation is performed from source excitation to geophone acquisition for about 500 μs [12].These prefetch operations are to ensure that some initial data is read before starting the continuous read.

Data Transfer Protocol Design
The common RS-485 transmission protocol cannot solve the data transmission congestion problem caused by earthquake transmission [12].In order to ensure the stability of data transmission and CPU resource utilization, a PPP transmission protocol is customized between the detector and the gateway.The protocol consists of frame header and tail delimiter, frame header, command mask, data length, data, and check code.The communication encoding is set to two bytes, the lower 3 bits are the protocol frame check code, the upper 13 bits are the node address, and the check method is CRC8, which is used to check all fields except the delimiter [12].

Equivalent Noise Test
After hardware debugging and software writing, PCB board production is carried out for actual verification testing.Figure 10 shows the data acquisition circuit board.The equivalent noise can reflect the minimum accuracy of the acquisition system [13].Test the electronic interference noise of the ADS1285 data acquisition circuit and A/D conversion circuit to ensure that the noise in this part of the circuit does not affect the acquisition of seismic signals with the minimum instrument resolution.with conversion.The test method is to short-circuit the input terminals of the three components to ground, start the A/D conversion output at a sampling rate of 4ksps, and compare it with the effective resolution of the instrument.The experimental detection results of the equivalent input noise of the host computer are shown in Figure 11.The noise distribution is shown in the figure, and the noise is within 0 to 1μV.The formula for calculating its equivalent noise is: where S represents the mean of the sampling sequence: The three components of the three circuit boards were selected for the equivalent noise test, the acquisition conditions were   4.096 ,  5 , and the crystal oscillator was 8.192MHz, and the calculation results are shown in Table 1, which proves that the noise suppression effect of the three-component VSP seismic acquisition system is good, and the average equivalent noise of the data acquisition system is less than 0.5μV.As shown in Table 1, the average value of the equivalent noise of the six component channels of the two circuit boards is 0.292μV, and the dynamic range is calculated.The dynamic range formula is as follows: 20 log( ) Among them, DR is the dynamic range, the unit is dB; VMAX is the maximum input signal, the unit is V; G is the gain, which is 1 in this formula;  is the minimum input signal, the unit is1μV, take the average value of 0.292μV, and calculate the dynamic range is 135dB, which meets the 110dB requirement in seismic exploration.
Under the same experimental conditions, the same equivalent noise test using 24-bit ADS1255 as the existing VSP exploration instrument on the market is shown in Figure 13.Compared with the equivalent noise of the ADS1255 chip, which is around 1μV, the equivalent noise of the ADS1285 reaches less than 0.5μV, and the 32-bit analog-to-digital conversion chip will greatly improve the ability to identify and extract weak signals.

Collection Stability Test
Through the given input signal, the error between the output signal quantity of the acquisition system and the given input signal quantity is compared to calculate the acquisition accuracy of the system.The output signal uses a precision signal source as the input signal of the system, which outputs  It can be seen that the collection accuracy reaches within 0.002%.In order to test the stability of the data collected by the system, the same input signal was collected for 15 consecutive times to 1.001503V to calculate the absolute value of the error between the collected signal and the input signal.The error range diagram is shown in Figure 12.It can be seen that the absolute value of the error is less than 5μV.

Harmonic Distortion Test
Test whether the signal conditioning circuit of each channel inside the circuit design produces distortion to the standard sinusoidal signal.Test whether the ADS1285 data acquisition circuit and A/D conversion circuit can correctly reflect the fidelity of the original signal [14].The test method will enter the self-test mode,and input a sinusoidal signal from the input terminal with a frequency of 30Hz and a peak-to-peak value of 3.37V, and set the ADS1285 to perform analog-to-digital conversion at a sampling rate of 4kHz, and collect the waveforms of each channel.As shown in Figure 15, the harmonic distortion test of the host computer is carried out.
Distortion calculation: The DFT transform of the measured sampling sequence Y is Xi (1 ≤ i ≤N), then the main frequency energy is: The harmonic energy is: Where M is the harmonic spectrum line energy number, then the distortion is: Calculating the test data in Figure 15, the distortion of the three detectors is less than -110dB, indicating that the acquisition node can condition the original signal with high fidelity.

Actual Vibration Testing
Connect the data acquisition circuit to the moving coil acceleration sensor, place the instrument on the ground and tap it to achieve micro-vibration.Set the sampling rate to 4kSPS, select 2048 sampling points, and set the gain to 1.The obtained data is shown in Figure 16 Show.It can be seen that under continuous micro-vibration, the image is clear and clean, the paragraph jumps crisply, without obvious noise interference, and the three-component channels are well synchronized.The amplitude of the waveform is at the microvolt level, the x-component vibration spectrum is lower than 200Hz, and the spectrum energy is concentrated.Below 60Hz, high-frequency noise is suppressed.There is no loss of data transmission, indicating that the data acquisition system has high reliability and is suitable for micro-vibration signal detection.

Conclusion
This article introduces a three-component seismic data acquisition design based on the ADS1285 analog-to-digital conversion chip.By using digital signal transmission and Ethernet-RS485 bus network system, compared with the traditional design, the resolution of weak signals is improved and the traditional problem is solved.The 24-bit analog-todigital conversion chip design has the problems of insufficient resolution, high power consumption and reduced noise.The test results show that the equivalent noise level of the threecomponent channel of the data acquisition system of this design can reach below 0.5μV and a dynamic range of 135dB, which increases the dynamic range by 5 to 8dB compared with existing detectors on the market.However, there is also 50Hz power frequency interference.The next step will be to conduct field testing in conjunction with the host of the seismic acquisition system, focusing on underground seismic detection, and designing a geophone suitable for seismic exploration in the field environment.

Figure 4 .
Figure 4. Simultaneous Acquisition of Multiple ADCs

Figure 6 .
Figure 6.Main Control Design Circuit

Figure 7 .
Figure 7. Block Diagram of ADS1285In the input interface setting, one channel inputs the detected analog signal, and the second channel inputs the standard sinusoidal signal[11].In the software configuration, enter the value of DR[2:0] in the editing register CONFIG0 to 0X04 to set the 4kSPS sampling rate, the value in MODE[1:0] to 0X00 to set it to high performance, the value in PHASE to 0X00, FILTR[ The value in 1:0] is 0x02 and is set as FIR filter; the value of MUX[2:0] in high-performance register CONFIG1 is 0x00 and is set as one channel, and the value of GAIN[2:0] in GAIN[2:0] is Set the PGA to double for 0x00, set the REF[2:0] value to 0x01 to 4.096V reference voltage, and the external input crystal oscillator to 8.192MHz

Figure 10 .
Figure 10.Front of the Data Acquisition Board

Figure 11 .
Figure 11.Back of the Data Acquisition Board

Figure 12 .
Figure 12.DC-DC Power Supply Board

Figure 13 .
Figure 13.Equivalent noise test for different ADCs stable DC signals with different amplitudes, and compares and detects the output digital signals.The results of 15 tests are shown in Figure 14 below.

Figure 16 .
Figure 16.Micro-vibration Test and Interception of X-component Vibration Amplitude and Spectrogram

Table 1 .
Equivalent input noise test data