Design and Implementation of Precision Phase Measurement Module Base on Digital Dual Mixer Time Difference

: Precise phase difference measurement is critical for distributed time synchronization systems. Aiming at the problem of how to realize the sub-nanosecond phase difference measurement of the time signal, the digital dual mixer time difference (DDMTD) measurement technology is used to measure the fine transmission delay and the two digital clock phase difference. Given the problem that it is difficult to generate a common clock source with fine frequency changes inside the FPGA chip, the Si5338 chip is used to generate 4 differential clocks, and the communication with the FPGA is completed through the I 2 C protocol, and the differential signal is converted into a single-ended clock source inside the FPGA as two The common standard frequency of clock signals with the same frequency and different phases, realize the amplification of the phase difference measurement range, making the measurement accuracy reach sub-nanosecond level.


Introduction
Both distributed real-time simulation systems and distributed coherent radars require high-precision time synchronization.Due to the extremely wide coverage of these facilities, the applicability of traditional point-to-point time synchronization methods is limited, and this distributed facility also poses a challenge to the synchronization accuracy that traditional time allocation systems can achieve [1].In 2008, the European Organization for Nuclear Research (CERN) proposed the White Rabbit (WR) technology, which was designed to achieve sub-nanosecond distributed clock synchronization and data transmission with deterministic delay, for application in accelerator synchronization control.WR clock synchronization technology is an extension of IEEE 1588-2008 (PTP), mainly aimed at improving the accuracy of PTP clock synchronization and increasing time synchronization accuracy by one order of magnitude to meet the needs of large-scale scientific infrastructure for time synchronization.This technology combines multiple mature technologies such as Synchronous Ethernet (Sync-E), Precision Time Protocol (PTP), and digital dual mixing, and is a technology that utilizes fiber optics to achieve highprecision time-frequency transmission.By using the WR-PTP protocol and digital dual mixing phase detector to enhance timestamp accuracy, the synchronization accuracy can reach sub-nanosecond level due to the ability to accurately calculate and compensate for line delay asymmetry.Due to its fully open source, strong universality, and high accuracy, WR technology has received increasing technical support from research institutions and commercial companies [2].Based on the White Rabbit protocol, the designers proposed an improved scheme for digital dual mixer time difference (DDMTD) amplification technology to automatically adjust propagation delay and maintain phase alignment, resulting in clock jitter and clock deviation less than 100 ps [3].
DDMTD is a digital system that theoretically can use a relatively low-frequency counter to measure the time difference between two digital clock signals at very low resolution.The system is essentially a digital phase detector with femtosecond time resolution.The main issue with this processing technology is its feasibility and accuracy when implemented on FPGA.Another issue is the horizontal phase noise caused by the environment in digital signals.This noise will endanger the fidelity of the clock and cause faults in the signal.This article mainly verifies the feasibility of implementing DDMTD on FPGA and achieves subnanosecond measurement accuracy [4].

Principle of Digital Dual Mixer Time Difference (DDMTD)
The digital dual mixer time difference (DDMTD) measurement technology is a development of the analog dual mixer time difference measurement (DMTD) technology.DMTD is very useful for characterizing the clock stability of two clock signals ( 1clk and 2 clk ) with the same nominal frequency.By using a common offset clock, DMTD performs analog mixing and down-converts the two input clocks to low frequencies.After low-pass filtering, the resulting signal can be used to estimate the phase difference between the two clock signals.

Analog Dual Mixing time Difference
Where 0 v is the frequency of the input clock, offset  is the phase shift of 2 clk relative to 1 clk , and the time difference between the two clocks is shown in the following equation: The phase function of the common clock source The two input clock signals defined in formulas ( 1) and ( 2 2 According to formulas ( 3) and ( 7):

Digital Dual Mixing time Difference
DDMTD uses digital mixing to generate an output clock signal with a frequency lower than the input clock signal.Figure 2 shows the working principle of DDMTD.

. DDMTD phase detection principle diagram
The working principle of DDMTD is shown in Figure 2, clka and clkb represent the local clock and recovery clock in the data stream, respectively.They have the same frequency but different phases.The auxiliary clock signal is generated by an external phase-locked loop, and there is a slight difference between the frequency of the auxiliary signal and the measurement signal frequency clka , clkb .The frequency relationship between them satisfies the following equation: After passing through a three-level D-flip-flop, the lowfrequency clocks N  times.Figure 3 shows that when N=1, the output clock signal is amplified three times in the clkc domain.As shown in Figure 3 .When it is high level, it happens to be the phase difference between the two clocks.Count the high and low levels using a 500MHz clock, and within half a cycle of the output signal, the total phase is 180 .According to formula (10), the phase difference between and can be calculated.
Where _ pos cnt is the count of the high-level of signal xor, _ neg cnt is the count of the low-level of signal xor.

Generation of Auxiliary Frequency
The key to DDMTD is the generation of auxiliary frequencies.Due to the frequency satisfying formula (9), there will inevitably be decimals, which is not easy to achieve with Verilog programming.The generation can be done in two ways: (1) Calling the PLL or MMCM of FPGA to generate an auxiliary clock, the clock frequency and the frequency of the measured clock ( a clk and b clk ) satisfy the relationship of formula (9), and this scheme is only applicable to the case of 1 5 N   .As the value of N increases, the frequency value of offset f and clka f become closer and closer.When 5 N  , the auxiliary clock frequency generated by this method was equal to clka f , and mixing effect could not be achieved at this time.
(2) Using clock chip Si5338 to generate auxiliary frequency.Si5338 is a high-performance, low jitter clock generator that can synthesize four user programmable clock frequencies.Si5338 adopts a two-stage synthesis architecture and highresolution MultiSynth technology, which can generate four independent frequencies from one input frequency.In addition to generating a clock, the input can also bypass the synthesis stage, allowing Si5338 to be used as a highperformance clock buffer or as a combination of buffer and generator.For applications that require frequency tuning, such as clock margin tuning, each synthesized frequency can be incremented or decremented by a user-defined step, with a minimum step of 1 ppm.Output-to-output phase delays are also adjustable in user-defined steps with an error of <20 ps to compensate for PCB trace delays or for fine tuning of setup and hold margins.The zero delay mode also helps to minimize input to output delay.
The configuration and operation of Si5338 are controlled by using the I 2 C interface to read and write RAM space.This device operates in a 7-bit addressing slave mode and can operate in standard mode (100 kbps) or fast mode (400 kbps), and supports burst data transmission with automatic address increment.The I 2 C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL).
To simplify device configuration, Silicon Labs provides ClockBuilder desktop software.This software has two purposes: to configure the optimal frequency division ratio for Si5338 based on the required frequency and to control the EVB.The optimal configuration can be saved in a text file from the software, which can be used in any system through I 2 C configuration.

Figure 5. Si5338 Frequency Configuration Diagram
As shown in Figure 5, four output frequencies can be set each time, with an accuracy of up to 9 decimal places.When N is taken as 5, 6, 7, and 8, the auxiliary clock frequencies correspond to 9.6969697MHz, 9.846153846MHz, 9.922480620MHz, and 9.961089494MHz, respectively, when the measured clock is 10MHz.After setting all the parameters in Figure 6, save the C Code Header File, convert the C Header source file into a Si5338.miffile using a Python program, and add this file to the Memory Initialization Files folder in the Vivado project.If the N value is different, multiple mif files can be added at the same time.When instantiating the Si5338IIC master module at the top level of the project, modify the mif suffix file name to call the corresponding mif file, and complete the configuration of the Si5338 chip inside the FPGA.

Simulation and Test Results
Using modelism simulation, when N=5, the two output clock cycles are amplified 33 times, with a high level meter value of 103 and a low level meter value of 722.The phase difference is calculated according to equation (10), indicating that the function of measuring phase difference through digital dual mixing can be achieved.
The test verification is implemented through the XC7k325 board of ALINX.The input FPGA clock is 200MHz, and two same frequency clocks with a difference of 10 º are generated through the MMCM of FPGA.When N takes different values, the generated bit stream file is burned into the development board, and multiple sum values of each N value are recorded in sequence, and the average value is calculated.are the counts of high and low levels respectively.The recorded data is averaged and recorded in Tables 1 and 2. As the N value increases, the probability of burrs appearing on the output clock edge also increases.As shown in Figure 9, when measuring the phase of two 10 MHz co frequency clocks, there will be burrs on the edge of the signal when N is taken as 13.When measuring the phase of two 125 MHz co frequency clocks, when N is taken as 12, burrs will appear on the edges of the signal.At this point, due to high and low level jumps, the counting will be inaccurate.When using MMCM to generate two 10MHz clocks with a phase difference of 10 º, the actual output phase difference of MMCM is 9.9 º.When N is taken as 3, 4, and 5, the measured phase difference is significantly different from the actual phase difference, and the measurement is not accurate at this time.As the N value increases to 8, the measured phase difference approaches 9.9 º.When N is taken as 9, the output clock signal is partially synchronized and cannot be measured (please provide an explanation).When N is taken as 12, the amplification factor is multiplied, and the counting clock frequency is 500MHz, with a period of 2ns, the measurement accuracy can reach 2 / 4097 488 fs  .

Conclusion
By comparing and analyzing multiple test results, the following conclusions can be drawn: (1) Small phase differences can be measured through digital dual mixing, and the measurement accuracy can reach sub-nanosecond level; (2) Choosing an appropriate auxiliary beat frequency can reduce or eliminate burrs and interference after mixing.When the amplification factor is small, there is an error in the measured phase difference; When the magnification is large, burrs appear on the edges, and the larger the magnification, the wider the width of the burrs.Therefore, it is necessary to choose a reasonable amplification factor.

Figure 1 .Figure 1
Figure 1.DMTD schematic diagram Figure 1 shows the working principle of DMTD.Assuming the two input clock signals 1 clk and

1
) are converted into lower frequency clock signals while maintaining their phase shift offset  unchanged.A counter can be used to measure the time difference between 1

Figure 3 .
Figure 3. Schematic diagram of enlarged measurement range when N=1 Two clocks clka and clkb with the same frequency but different phase, triggered by an auxiliary clock clkc , just linearly amplify the measurement range of clka and clkb by 2 1N  times.Figure3shows that when N=1, the output clock signal is amplified three times in the clkc domain.As shown in Figure3, xor is the XOR operation of clock signals , xor is the XOR operation of clock signals DMTD clka and DMTD clkb

Figure 4 .
Figure 4. Digital Mixing Phase Discrimination Frame Diagram The block diagram of the digital dual mixing phase discriminator is shown in Figure 4. Clocks of the same frequency but different phases are generated by the internal MMCM of the FPGA, and the common clock source is communicated with the Si5338 clock chip through the I 2 C protocol by the Si5338 control module.Storage files are configured to generate a common clock source for the Si5338 clock chip.The DDMTD module completes the mixing and low-pass filtering of two same-frequency clocks.The phase counting module counts the high and low levels of the two output signals after XOR, and measures the phase difference using equation (10).

Figure 7 .
Figure 7. Upper board test diagram

Figure 7
Figure7shows the signals captured by Vivado's Integrated Logic Analyzer after the program is loaded.After burning the bitstream file into the development board, a trigger condition is required to display all desired waveforms.Here, the rising edge of Q3 is selected as the trigger condition.Due to the fact that the 4-way clock (differential to single-ended) generated by the FPGA external clock chip Si5338 has decimals, it

Figure 8 .
Figure 8. ILA Grasping Half Cycle Waveform Amplification As shown in Figure 8, out Q is the XOR of 3 Q ( in Figure 2) and 6 Q (in Figure 2), : 0] _ [31 pos cnt and

Figure 9 .
Figure 9. Jitter appear on the edge of the signal Qout when N increases to a certain value

Table 1 .
Phase Counting Measurement of 500MHz to 10MHz Signal

Table 2 .
Phase Counting Measurement of 500MHz to 125MHz Signal N 2 N 2 N +1When using MMCM to generate two 125MHz clocks with a phase difference of 10 º, the actual output phase difference is 11.25 º.When N is taken as 11, the amplification factor is