Research on Low Power BIST Based on LFSR Reseeding


  • Zuo Peng



Test vector seed reordering, LFSR reseeding technology, Test vector generation, Low power consumption, BIST, Test response analysis.


With the increasing scale and complexity of the internal circuit, the function of the chip is more powerful, but it will bring serious problems to the test of the chip. The internal power consumption of the chip in the test mode is much higher than that in the normal working mode, especially in the process of built-in self-test, the excessive power consumption will damage the circuit under test and lead to the failure of the chip. The low power test vector generation technology reduces the test power by preprocessing the test vector set. However, the modification of the test vector set results in the low failure coverage in the test process. LFSR replaying technology is a common method of generating test vectors in built-in self-test. It can improve the coverage of test faults by loading test vector seeds into linear feedback shift register. However, while improving the fault coverage, the technology will generate high test power consumption in the circuit under test. In design for testability (DFT), it is a hot topic to generate low-power test vectors by combining LFSR reseeding technology with low-power test vector generation technology. Aiming at the problem of high power consumption caused by test vectors in built-in self-test, this paper proposes a low power test vector generation method based on LFSR reseeding. On the basis of studying the influence of test vector on dynamic test power consumption, the linear correlation between test vector seed and test vector is analyzed deeply. A model of dynamic test power consumption optimization based on Hamming distance sorting test vector seed is proposed to realize the design of low-power test vector seed generation algorithm. Combined with LFSR reseeding technology, a low-power test vector generator based on test vector seed sorting is designed. The simulation design of test vector generator is based on ISCAS85 and ISCAS89. The experimental results show that the total number of test vector seed storage bits is reduced by 64.39%, the average fault coverage is 97.42%, the average area overhead is 4.32%, and the dynamic test power consumption is reduced by 44.21%. Compared with other schemes, the proposed low-power test vector generation technology based on LFSR reseeding has some comprehensive advantages in reducing the number of seed storage bits, improving fault coverage, reducing circuit area overhead and reducing power consumption.


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A. Krishnamachary, J. A. Abraham. Effects of multi-cycle sensitization on delaytests[C]. 16th International Conference on VLSI Design, 2003: 137-142.

R. Hamza. A novel pseudo random sequence generator for image cryptographic applications[J]. Journal of Information Security and Applications, 2017, 35(19):119-127.

A. Jas, C. V. Krishna, N. A. Touba. Hybrid BIST based on weighted pseudo-random testing: a new test resource partitioning scheme[C]. Proceedings 19th IEEE VLSI Test Symposium, 2001: 2-8.

K. Balaguru, T. V. U. Kiran Kumar. Test data compression architecture for low power VLSI testing[J].World Applied Sciences Journal, 2014, 29(8):1035-1038

P. Rosinger. Dual multiple-polynomial LFSR for low-power mixed-mode BIST[J]. IEEE Proceedings of Computers & Digital Techniques, 2003, 37(9): 47-51.

Sun Xiubin, Research on Built - in - test (BIST) Method for fault diagnosis of mixed signal circuits,2004

G. Vellingiri, R. Jayabalan. An improved low transition test pattern generator for low power applications[J]. Design Automation for Embedded Systems, 2017, 21(7):1-17.

G. Vellingiri, R. Jayabalan. An improved low transition test pattern generator for low power applications[J]. Design Automation for Embedded Systems, 2017, 21(4):247-263.

P. S. Dilip, G. R. Somanathan, R. Bhakthavatchalu. Reseeding LFSR for Test Pattern Generation[C]. 2019 International Conference on Communication and Signal Processing (ICCSP), 2019: 0921-0925.

B. Zhou, Y. Ye, X. C. Wu, et al. Reduction of test power and data volume in BIST scheme based on scan slice overlapping[C]. IEEE. Int. Symp. on Circuits and Systems, 2009: 2737.

Jing G, Yi L, Yu X Y. Research and Simulation Test Base on LFSR Reseeding Test Compression Technology[C]. The 4th International Symposium on Computational Intelligence and Industrial Applications, 2010: 168-173.

J. Praveen, M. N. Shanmukha Swamy. BIST-Based Low Power Test Vector Generator and Minimizing Bulkiness of VLSI Architecture[J]. Journal of Circuits Systems and Computers, 2018, 27(5):1850078-1850082.

A. S. Abu-Issa. Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2018, 65(3): 361-365.

K. Thilagavathi, S. Sivanantham. Two-stage low power test data compression for digital VLSI circuits[J]. Computers & Electrical Engineering, 2018, 71: 309-320.

G. Zhang, Y. Yuan, F. Liang, et al. Low Cost Test Pattern Generation in Scan-Based BIST Schemes[J]. Electronics, 2019, 8: 314.

Zhang, X W, Li M, Hu J. Optimization and Implementation of AES Algorithm Based on FPGA[C]. 2018 IEEE 4th International Conference on Computer and Communications, 2018: 2704-2709.







How to Cite

Research on Low Power BIST Based on LFSR Reseeding. (2022). Academic Journal of Science and Technology, 3(2), 203-208.

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