Research on Innovation Path of 3D Transistor Architecture

Authors

  • Langhao Wang

DOI:

https://doi.org/10.54097/9vkzre17

Keywords:

Integrated Circuit; MOSFETs; FinFET; GAAFET; CFET.

Abstract

The exponential growth of the integrated circuit (IC) industry, historically governed by Moore’s Law, now faces challenges as traditional silicon based planar MOSFETs approach their fundamental physical limits. Among all solutions to sustain IC development, three-dimensional structural innovations in transistor architecture present a key viable pathway. This paper analyzes the evolution from planar structures to the three leading variants that have shown successful progress and promising potential: Fin Field-Effect Transistors (FinFET), Gate-All-Around FETs (GAAFET), and Complementary Field-Effect Transistors (CFET). Each variant has unique strengths and exists at a different stage of maturity and industry adoption. Through its tri-gate design, FinFET has mitigated leakage and improved electrostatic control. Through its gate-all-around design, GAAFET offers enhanced electrostatic control, which boosts on-current by reducing quantum capacitance effects and improving carrier mobility. Looking ahead to beyond the 1nm node, CFET vertically stacks n-type and p-type transistors and promises unprecedented reductions in circuit footprint. However, while FinFET nears its limits and GAAFET emerges as its successor, future efforts must tackle CFET’s key manufacturing and thermal hurdles to enable further advances.

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Published

13-03-2026

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Section

Articles

How to Cite

Wang, L. (2026). Research on Innovation Path of 3D Transistor Architecture. Academic Journal of Science and Technology, 19(3), 222-228. https://doi.org/10.54097/9vkzre17