FPGA ‐ Based Improved Sobel Operator Edge Detection

: Image edge detection is an important field in image processing, with its primary goal being to identify edge information of various objects in images. Traditional edge detection programs are mostly executed serially, resulting in low detection efficiency. This paper proposes an FPGA-based improved Sobel operator edge detection method, harnessing the parallel processing capability of FPGA to enhance detection efficiency. Building upon the Sobel operator in edge detection algorithms, this method increases the convolution calculation dimensions of the Sobel operator, expanding it from 2 directions to 8 directions for more precise edge information. Images captured by OV5640 are processed within the FPGA and displayed via VGA. Compared to other edge detection algorithms, the FPGA-based improved Sobel operator edge detection method efficiently and rapidly detects image edges, ensuring stable image display and accurate edge information.


Introduction
With the widespread application of digital images in modern society, image edge detection has become increasingly important as a core task in the fields of computer vision and image processing.From autonomous driving to medical image analysis, image edge detection provides critical information for various applications, helping us understand the shapes and structures of objects.However, traditional edge detection methods face challenges when dealing with various types of images and noise [1].
In this context, this paper presents an FPGA-based improved Sobel operator edge detection method to enhance the performance and efficiency of edge detection.The Sobel operator is a common edge detection method, but it may yield suboptimal results in certain situations.Our research aims to address these issues and provide new insights for further research in the field of image edge detection.
The structure of the FPGA-based improved Sobel operator edge detection, as shown in Figure 1, consists mainly of four modules: the image capture module, data storage module, image processing module, and VGA display module.
The FPGA section uses ALTERA's Cyclone IV series chip, model EP4CE10F17C8.The image capture module employs an OV5640, which features a 5-megapixel high-definition camera with a fixed focus lens.The VGA display module utilizes VGA driver control to transmit the processed images to the monitor

Image Capture Module
The image capture primarily utilizes the OV5640 highdefinition camera, which has an actual photosensitive array of 2592×1944 (5 megapixels), allowing it to capture a wealth of image information and support VGA display output of image data [2].The sensor integrates numerous image processing circuits internally, including automatic exposure control, automatic white balance, ISP (Image Signal Processor), etc., enabling basic processing of the captured images.
The operational principle of OV5640 is as follows: Firstly, the camera's clock is provided by XVCLK, triggering the reset signal and initiating the camera to begin image capture after initializing registers.Secondly, it coordinates the PCLK (pixel clock), HREF (horizontal reference signal), and VSYNC (vertical synchronization signal) through timing logic to achieve synchronized transmission with the camera's digital image signal.Finally, the image is transmitted to the host computer for display via the 8 data output ports D7-D0 on the DVP interface.The functions of OV5640 are depicted in Figure 2.

Image Storage Module
SDRAM is a type of Synchronous Dynamic Random-Access Memory, where 'synchronous' means that the clock frequency matches the clock frequency of the processor system bus.To ensure that data is not lost, the memory array needs to be constantly refreshed.SDRAM allows for nonlinear storage of data, and read/write addresses can be freely chosen [3].As shown in Figure 3, the storage space of SDRAM is divided into 4 L-Banks.When addressing, one L-Bank needs to be specified, and then the desired row and column can be selected within the chosen L-Bank.
The SDRAM chip model used in this case is 'HY57V2562GTR,' with a capacity of 256Mbit and a 16-bit data bus width.The Storage Structure is shown in Figure 4.

Grayscale Processing
To perform edge detection, it is necessary to process the pixel grayscale values of an image.There are several mainstream methods for this: Due to the fact that the grayscale image displayed using the Y component in the third method exhibits stronger contrast and a more realistic display compared to the grayscale images displayed in the first two methods, this system adopts the third method for grayscale image processing.

Median Filtering
Median filtering is a common spatial domain filtering technique primarily used for noise reduction and image smoothing.Unlike pixel-based weighted averages, it relies on pixel value sorting [5].The working principle can be divided into three steps: The first step involves defining a sliding window, typically in the shape of a square or rectangle, and then sliding this window across the image.In this case, a 3x3 window size is used, as shown in Figure 5c).
In the second step, at each window position, the pixel values within the window are sorted, usually in ascending or descending order, resulting in an ordered list of pixel values.
In this case, an ascending order is used.The Sobel operator is a commonly used convolution kernel in image processing and edge detection.It calculates gradient magnitude and compares it to a threshold, making it a classic edge detection algorithm [6][7][8][9][10].The traditional Sobel edge detection uses operators that are typically divided into two directions, as shown in Figure 5a) and Figure 5b): the xdirection for horizontal edge detection and the y-direction for vertical edge detection.Performing convolution operations with the two directional operators on the 3x3 image matrix shown in Figure 5c), you can obtain the gradients G90° (in the x-direction) and G180° (in the y-direction) as described by equations ( 6) and ( 7): By squaring G90° and G180° separately and then taking the square root, you obtain the gradient magnitude G as shown in equation (8).
When the gradient magnitude G exceeds the predetermined threshold T, the image edge, denoted as Edge, is set to 1.This signifies that the pixel point is an edge point.Otherwise, if G is less than or equal to the threshold T, the image edge, Edge, is set to 0, indicating that the pixel point is not an edge point, as described in equation ( 9).Traditional Sobel edge detection is known to have limitations in terms of the limited dimensionality of convolution factors, which can result in lower accuracy in image detection and a lack of richness in capturing fine edge details.
Using the parallel processing capabilities of FPGA, convolution operations can be performed with the eightdirectional operators on the 3x3 region centered around the pixel to be detected, as described in equation ( 10) to (17 The gradient magnitude G is obtained by summing the squares of the convolution results from all eight directions, as described in equation ( 18)-( 20): The comparison of the gradient magnitude G with the preset threshold T, where if G is greater than or equal to the threshold T, Edge is set to 1; otherwise, the image Edge is set to 0. In this case, the chosen threshold T is 250, as shown in equation ( 21).

VGA Display
The VGA (Video Graphics Array) video graphics array is a computer display standard introduced by IBM in 1987 that uses analog signals for data transmission.The VGA interface is a dedicated interface for outputting data that conforms to the VGA standard.This interface consists of 15 pins, organized into 3 rows with 5 holes each.It is used to transmit analog signals for red, green, blue, as well as horizontal and vertical synchronization signals.VGA monitors are known for their low cost, simplicity of structure, and versatility [11][12].
The operating principle of a VGA monitor is to start scanning from the upper-left corner of the screen, moving from left to right, and repeating this left-to-right scan at the beginning of each new row after completing a row.After scanning each row, it uses a row synchronization signal for synchronization.Once all rows are scanned, it forms a frame and uses a field synchronization signal for field synchronization.The timing diagram for row synchronization is shown in Figure 7, and the timing diagram for field synchronization is shown in Figure 8.

PLL Module
In FPGA design, due to the different frequency requirements of various modules, a PLL (Phase-Locked Loop) module is commonly used to perform clock signal division or multiplication on existing clock signals.In the context of improving the Sobel edge detection algorithm, there are the following clock signal requirements: The I2C register configuration module requires a 50MHz clock.The SDRAM controller requires a 100MHz signal, A 65MHz phase-offset clock is also needed.The VGA display controller module also requires a 50MHz clock signal.To meet the clock signal requirements of the entire system, a PLL IP core is employed.This PLL IP core uses the external 50MHz clock signal as a reference to generate three different clock signals with distinct frequencies.

System Testing and Validation
To validate the effectiveness of the improved Sobel algorithm proposed in this paper for image edge detection, Verilog HDL code was developed using the Quartus II development environment.The code was compiled and loaded through JTAG for programming the FPGA.The experimental environment and results are shown in Figure 9.
In Figure 9: A) Represents the original image.In this experiment, the OV5640 camera was used for edge detection of flowers.B) Shows the grayscale image after grayscale processing.C) Displays the grayscale image after median filtering.D) Illustrates the result of traditional unimproved Sobel algorithm applied to flower image edge detection.It can be observed that the image contains a considerable amount of noise and false edges, and some edge information is lost or discontinuous in both the x and y directions.E) Presents the result of this design.It is evident that both edge continuity and image detail richness are superior to the traditional Sobel algorithm.Additionally, local noise and false edges are effectively controlled, resulting in better edge continuity.

Conclusion
This paper addresses issues with traditional Sobel edge detection, such as limited convolution factor dimensions, resulting in lower accuracy in image detection and a lack of richness in capturing fine edge details.To overcome these limitations, an improved Sobel edge detection algorithm is proposed, which increases the dimensionality to eight directions and is implemented on an FPGA.Through onboard experiments, the feasibility of this improved algorithm is verified.Compared to traditional algorithms and software implementations, this paper achieves higher accuracy, captures richer image edge details, and offers improved computational speed.It holds significant practical value in the field of image processing.

Figure 1 .
Figure 1.FPGA-Based Improved Sobel Operator Edge Detection System Block Diagram

Figure 2 .
Figure 2. OV5640MRSL block diagram (1) Luminance Method: This approach involves calculating the luminance by linearly combining the red, green, and blue channels with weighted coefficients.It is designed based on the varying sensitivity of the human eye to different colors.Typically, higher weight is assigned to the green channel because the human eye is more sensitive to green.Its mathematical expression is: Y 0.299 R 0.587 G 0.144 B 1 In this context, where Y represents brightness, and R, G, B respectively represent the values of the red, green, and blue channels.(2) Component Method: In the component method, only one-color channel from a color image is used to generate a grayscale image.The pixel values of the selected channel are used as the pixel values of the grayscale image.In this case, each pixel's grayscale value contains information from only one-color channel.As needed, the generated grayscale values are then mapped to the range of 0 to 255, resulting in a grayscale image.(3) Convert the three-channel RGB image data into a Ycbcr image using addition and multiplication operations [4], and then display the image using the Y component.The image transformation algorithm is defined by equations (2), (3), and (4) as shown.If a calculated value is negative, it is set to 0. Y 0.183 R 0.614 G 0.062 B 16 2 Cb 0.568 B Y 128 3 Cr 0.713 R Y 128 4

Figure 4 . 5 Figure 5 .
Figure 4. HY57V2562GTR Hardware Circuit DiagramThe third step entails selecting the middle value from the sorted list as the new pixel value for the current pixel position.Its mathematical expression is: F x, y median g s, t , s, t ∈ 5