Implementation of miniaturized ACARS system based on FPGA

Authors

  • Chunlan Luo
  • Lecai Cai
  • Shiyong Yang

DOI:

https://doi.org/10.54097/jceim.v10i2.7875

Keywords:

ACARS, ADC, DDC, Signal processing element

Abstract

ACARS system is an aircraft communication addressing and reporting system, which plays an important role in the transmission of aircraft identity information. It is mainly used for radio communication between aircraft and ground base stations. The signal processing of the traditional ACARS system adopts two methods. One is to demodulate the baseband signal by analog method, and then decode the baseband signal by PC. This method will bring great cost and require more frequency conversion levels (frequency conversion times), resulting in complex circuits and difficult debugging. The other is to use ADC to sample the analog intermediate frequency signal and then directly process the digital intermediate frequency signal. This method leads to the large consumption of resources in the later processing unit, which brings great pressure to the processing capacity of the later digital signal processor. Digital down conversion (DDC) is a key technology in the field of communication detection. It reduces or removes the carrier frequency of the signal by spectrum shifting, and filters and extracts the signal by decimation filter to match the rate requirements of the subsequent receiver. DDC is widely used in software radio, ultra-wideband radar and other fields. The principle is that the input digital intermediate frequency signal passes through a mixer composed of two multipliers, and the digital control oscillator simultaneously generates two orthogonal local oscillator signals, which are multiplied to obtain Q and I signals respectively. Then, the digital baseband signal is output by decimation through the latter filter, which has the advantage of reducing the data rate.

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Published

23-04-2023

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Articles

How to Cite

Luo, C., Cai, L., & Yang, S. (2023). Implementation of miniaturized ACARS system based on FPGA. Journal of Computing and Electronic Information Management, 10(2), 41-44. https://doi.org/10.54097/jceim.v10i2.7875

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