A Quantized CNN for Traffic Sign Recognition Deployed on FPGA

Abstract

With the development of intelligent transportation systems, traffic sign recognition plays a key role in autonomous driving and driver assistance systems. The performance of traffic sign recognition algorithms directly impacts the safety of vehicles during operation. Although traditional 32-bit floating-point convolutional neural networks (CNNs) offer the advantage of high recognition accuracy, their substantial number of parameters and computational intensity make them difficult to deploy directly on resource-constrained devices like in-vehicle FPGAs. Based on this, this paper proposes a lightweight CNN model for edge computing. At the algorithmic level, a VGG-like straight-line network structure with 5 convolutional and 4 pooling layers is designed. Employing 4-bit quantization-aware training (QAT), pseudo-quantization nodes are embedded into the forward training process, enabling the network to maintain discriminative capability within the 4-bit discrete space. At the toolchain level, an end-to-end pipeline from PyTorch → QAT → HLS → bitstream is constructed. It supports one-click weight/activation bit-width pruning and RTL generation. The final generated bitstream file can be directly applied in FPGA deployment. Experiments were conducted on the GTSRB dataset. The final quantized model achieved a test accuracy of 87%, with a model size of only 0.15 MB. The hardware was deployed on a Xilinx Zynq-7020 SoC, with resource utilization falling within an acceptable range for the chip. The results indicate that the proposed method achieves an excellent balance among accuracy, resource consumption, and power usage, offering an efficient, automated, and easily deployable hardware-friendly solution for traffic sign recognition at the edge.