FPGA Design and Performance Evaluation of a Bus Arbitrator Based on Dynamic Priority Adjustment

Yibo Wang

doi:10.54097/c51j5715

Authors

Yibo Wang School of Electronic and Information Engineering, Tongji University, Shanghai, 201800, China

DOI:

https://doi.org/10.54097/c51j5715

Keywords:

Dynamic priority, Network-on-chip, Bus contention, Real-time systems.

Abstract

With the continuous advancement in system-on-chip (SoC) integration, balancing real-time responsiveness and fairness in bus access among multiple master devices has become essential for improving the overall performance and energy efficiency of complex SoCs. This study designs and implements a dynamic priority bus arbiter based on a multi-parameter weighting scheme that incorporates four factors: priority, waiting time, resource demand, and an emergency flag.This approach enables arbitration decisions that achieve high real-time performance, fairness, and low resource overhead. By establishing a test platform on Vivado for synthesis and simulation, the experimental results demonstrate that the proposed arbiter reduces the average grant delay to 1.82 ns and responds to urgent requests within 1.34 ns at a clock frequency of 500 MHz. While effectively controlling the logic resource utilization and power consumption, the arbiter ensures both practicality and superior fairness compared with conventional static arbitration strategies. This research is of great significance in promoting the application of next-generation intelligent computing chips in real-time-sensitive scenarios such as autonomous driving and edge computing.

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