MAO, Chenyang. Design and implementation of reorder buffer in superscalar pipeline processor. Academic Journal of Science and Technology, [S. l.], v. 20, n. 2, p. 289–297, 2026. DOI: 10.54097/bhcm1856. Disponível em: https://drpress.org/ojs/index.php/ajst/article/view/34094. Acesso em: 30 apr. 2026.