Design and implementation of reorder buffer in superscalar pipeline processor

Abstract

With the increasing demand for high performance and low power consumption in System-on-Chip (SoC) scenarios such as mobile terminals and servers, superscalar processors have become the core computing unit of high-performance SoCs by virtue of their multi-instruction parallel capabilities. However, the out-of-order execution mechanism of superscalar processors leads to contradictions between "out-of-order completion" and "in-order commit" of instructions, as well as difficulties in state recovery when branch prediction fails or exceptions occur. To solve these problems, this paper designs and implements a Reorder Buffer (ROB) module for 4-way issue superscalar pipelines. The ROB module adopts a parameterized design (data width 64bit, depth 32 entries) to realize functions such as instruction temporary storage, in-order commit, data forwarding, branch flush, and exception handling. Functional verification is carried out, covering 9 core scenarios including basic instruction issue, execution result writeback, branch flush, and post-flush instruction re-issue. Based on the 7nm FinFET process library for logic synthesis, the results show that the module achieves complete sequential convergence (slack 0.003ns) with a maximum operating frequency of 1607.72MHz, a total area of 10760.880μm², and a total dynamic power consumption of 4.6127mW. This ROB module can stably support the out-of-order execution and in-order commit of 4 instructions per cycle, providing a reliable core structure for high-performance 4-way superscalar processors.