Impact of Power, EMI, and SET on VLSI NOR Circuits with Collaborative Hardening Approaches

Yicheng Duan

doi:10.54097/t4w2gn62

Authors

Yicheng Duan

DOI:

https://doi.org/10.54097/t4w2gn62

Keywords:

NOR circuit, Power Consumption, Electromagnetic Interference (EMI), Single-Event Transients (SET), Synergistic Effects.

Abstract

Under deep submicron and nanoscale VLSI process conditions, chip reliability design has become equally critical as performance and power consumption. As a fundamental building block of SRAM, latches, and various combinational logic circuits, the stability of NOR gates directly determines the reliable operation of chips. This paper focuses on investigating the impacts of power consumption (static and dynamic), electromagnetic interference (EMI), and single-event transients (SET) on the performance of NOR circuits, analyzing both their individual effects and the coupling mechanisms under concurrent interactions. Findings reveal that excessive power consumption induces heating and compresses noise margins; EMI compromises signal integrity through coupling; and SET can trigger transient errors or even soft errors. By systematically examining the mechanisms of these phenomena in light of advanced process node characteristics, corresponding countermeasures are proposed, including circuit-level optimization, layout design methods, and system-level protection strategies. Through a comprehensive study of their synergistic effects, a cross-level, multi-dimensional collaborative design paradigm is further proposed to enhance the reliability of NOR circuits in complex environments, providing implementable theoretical support and engineering pathways for highly reliable chip design.

Downloads

Download data is not yet available.

References

[1] Z. Tan, L. Zhao, J. Wang, et al. “Interfacial and electrical properties of HfAlO/GaSb metal-oxide-semiconductor capacitors with sulfur passivation”. Chinese Physics B, 2014, 23 (01):431-435.

[2] P. Xu and Z. Pan, "Collaborative Applying the Ultra-low-k Dielectric and the High-k Dielectric Materials for Performance Enhancement in Coupled Multilayer Graphene Nanoribbon Interconnects," IEEE Journal of the Electron Devices Society, vol. 8, pp. 200-212, 2020.

[3] S. G. Narendra and A. P. Chandrakasan, “A. Leakage Dependence on Input Vector,” in Leakage in Nanometer CMOS Technologies, vol. II, S. G. Narendra, Y. Ye, S. Borkar, V. De, A. Chandrakasan, Eds. Boston, MA: Springer, 2006, pp.21-39.

[4] N. S. Kim et al., "Leakage current: Moore's law meets static power," in Computer, vol. 36, no. 12, pp. 68-75, Dec. 2003.

[5] Y. Wang, F. Liu, Y. Cao, et al. “Reliability study and modelling development of FinFET devices,” 2025, 25 (05): 66-74. (in Chinese)

[6] J. M. Redouté, M. Steyaert, EMC of Analog Integrated Circuits. Dordrecht: Springer, 2010.

[7] P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Transactions on Nuclear Science, vol. 50, no. 3, pp. 583-602, Jun. 2003.

[8] P. Roche, J. L. Autran, G. Gasiot and D. Munteanu, "Technology downscaling worsening radiation effects in bulk: SOI to the rescue," in 2013 IEEE International Electron Devices Meeting, Washington, DC, USA, pp. 766-769., Dec. 2013

[9] Reddy T V, Nakhate S. Radiation hardened by design technique to mitigate single event transients in combinational logic circuits [C]. 2017 International Conference on Recent Innovations in Signal processing and Embedded Systems (RISE), Bhopal, India, pp. 342-347, 2017.

[10] M. Fu. “Research on Radiation Hardening Technology Base on 28nm CMOS Integrated Circuit ,” M.S. thesis, University of Electronic Science and Technology of China, Chendu, China, 2024. (in Chinese)

[11] J. D. Black, P. E. Dodd and K. M. Warren, "Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction," IEEE Transactions on Nuclear Science, vol. 60, no. 3, pp. 1836-1851, Jun. 2013.

[12] S. S. Sapatnekar, "Overcoming Variations in Nanometer-Scale Technologies," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 1, pp. 5-18, Mar. 2011.

[13] H. Xiang. “Research and Design of Thermodynamic Simulation and Optimization Methods in Multi-Physical Field Co-simulation,” M.S. thesis, University of Electronic Science and Technology of China, Chengdu, China ,2025. (in Chinese)