Research on Power Consumption and Reliability of Digital Circuits Based on CMOS Electrical Characteristics

Abstract

This paper focuses on the evolution and optimization of CMOS devices, systematically reviewing the core characteristics of three typical device architectures: planar MOS devices, FinFETs, and MBCFETs. Subsequently, an in-depth analysis is conducted: planar MOS devices achieve switching by regulating carrier concentration via the electric field effect and are widely used in digital and analog circuits; FinFETs face challenges such as surging power consumption and declining reliability during scaling, and optimization suggestions are proposed from four aspects—low-power design, exploration of new material processes, architectural innovation, and establishment of a collaborative evaluation system; MBCFETs adopt a gate-all-around (GAA) architecture with a multi-layer channel stacking structure, offering more comprehensive gate wrapping and significant advantages in current drive capability and reduced parasitic capacitance, yet they also confront challenges such as epitaxial growth defects and increased complexity in the replacement metal gate (RMG) process. Furthermore, the article compares the performance and limitations of these three devices in a tabular format. The study elucidates the technological logic behind the evolution of CMOS from planar to 3D architectures, providing references on device characteristics for the semiconductor industry and aiding in understanding the application boundaries of different structures.