Low-Power MCUs: Power Modeling, Estimation, and Optimization

Abstract

Ultra-low-power microcontroller units (MCUs) are the foundation of IoT, wearable devices, and sensor networks, where energy efficiency directly determines system lifetime and reliability. This paper reviews power modeling, estimation, and optimization techniques tailored for low-power MCUs. Power consumption is analyzed across dynamic, short-circuit, and leakage components, with the fundamental relation of dynamic power expressed in (1). Estimation approaches at multiple abstraction levels—transistor-level, gate-level, RTL, and system-level—are compared in terms of accuracy, turnaround, and applicability. Gate-level power analysis, supported by SAIF-based switching activity, remains the reference standard, while RTL and system-level estimation enable rapid design-space exploration. Figure 1 illustrates the classical MCU pipeline structure, highlighting how switching activity from CPU, peripherals, and memory contributes to overall power. Optimization methods such as clock gating, power gating, dynamic voltage and frequency scaling (DVFS), near-threshold computing, approximate computing, and energy-aware logic synthesis are evaluated with their respective trade-offs in performance, energy savings, and design complexity. Recent trends emphasize machine learning–assisted estimation, automated power-intent synthesis, and hardware–software co-optimization. This comprehensive survey concludes that achieving decade-long MCU lifetimes requires integrating accurate modeling, fast estimation, and adaptive optimization strategies for real-world workloads.