Delay-Optimized Design of a 4-Bit Absolute Value Detector Energy-Efficiency Analysis for Embedded Signal Processing

Abstract

In low-power digital signal processing and embedded systems, the absolute value detector serves as a fundamental arithmetic unit whose performance directly impacts system efficiency. This paper proposes a delay-energy co-optimization design methodology for a 4-bit absolute value detector based on the logical effort method. Through critical path analysis, we identify the conditional increment module as the primary bottleneck and leverage the constraint excluding the input -8 (minimum 4-bit two's complement value) for structural optimization. The traditional implementation exhibits a 13-stage logic gate critical path with a minimum delay of 68.5τ. By treating -8 as a don't-care term in our custom adder design, we significantly simplify logic expressions. This reduces the critical path from 13 stages to 7 stages and lowers the minimum delay to 43τ, reaching 37% performance improvement. The logical effort per stage increases from 1.96 to 2.44, approaching the ideal operating point. For energy optimization, voltage scaling is employed under the constraint that delay remains within 1.5× the minimum value. Reducing the supply voltage from 1V to 0.775V yields 40% energy reduction at the cost of 50% delay increase. Key contributions include: (1) A constraint-driven structural optimization methodology; (2) A complete design flow from theory to implementation; (3) Validation of voltage scaling for energy efficiency under delay constraints. This approach demonstrates excellent implement ability in standard CMOS processes and offers valuable insights for arithmetic unit design in low-power embedded systems.