A Verilog-Based Configurable Multi-Width Asynchronous FIFO Design

Abstract

With the rapid development of integrated circuits, asynchronous FIFO, as a core component in digital system design, plays a significant role in data transmission and storage across clock domains. This paper designs a configurable bit-width asynchronous FIFO system on the Verilog platform that supports data widths of 8, 16, 32, and 64 bits. The system is partitioned into several key modules, including a write control module, a read control module, a storage module, a cross-clock pointer synchronization module, a bit width configuration module, and a top-level module. Functional verification and performance evaluation are carried out employing functional simulation, with comparative tests conducted under various write/read clock frequencies and bit-width configurations. The results show that under different write clock and read clock frequencies, this design can complete data transmission without loss or out-of-order, with the delay within a controllable range, and it can still maintain a high throughput efficiency even at a high write rate. This design can maintain the advantage of cross-clock domain transmission of asynchronous FIFO while flexibly adjusting the data width through hardware parameterization or runtime configuration, thereby adapting to more application requirements and improving system universality and resource utilization.