Designs of Low-Power Static Random-Access Memory
DOI:
https://doi.org/10.54097/r5ncc809Keywords:
Low-power SRAM, write/read-assist, multi-port SRAM, GAA nanosheet, RibbonFET.Abstract
With the fast development of big data, Internet of Things (IoT), and edge computing, the memory systems are required to the highest ever, in which the performance and energy efficiency have significant impacts on the overall system capability. Three things about SRAM make it ideal for on-chip storage and cache memories, It features high read and write speeds, low dynamic power consumption for reading and writing, and a mature process. In this paper, we give an all-encompassing review of low-power SRAM design techniques, including circuit-level and architectural innovations along with the emerging Computing-In-Memory (CIM) paradigm. Techniques include novel circuit methodologies such as read/write-assist, as well as emerging transistor technologies like GAA nanosheets. This survey reviews techniques to reduce the dynamic and leakage power consumption, enhance writability and reliability in low-voltage operation, and minimize the energy overhead associated with data movement. This work systematically investigates conventional and emerging methods and offers insights into how to design energy-efficient SRAM for next-generation portable and AI-centric platforms.
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[1] Ahmad S, Gupta MK, Alam N, Hasan M. Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016, 24(8): 2634-2642.
[2] Rzepa G, et al. Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node. 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022: 15.1.1-15.1.4.
[3] Zhao Q, Peng C, Chen J, Lin Z, Wu X. Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020, 28(3): 848-852..
[4] He Y, Zhang J, Wu X, Si X, Zhen S, Zhang B. A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(10): 2344-2353.
[5] Lin Z. Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. IEEE Journal of Solid-State Circuits, 2021, 56(9): 2832-2844.
[6] Si CX. A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. 2020 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2020: 246-248Kim D, et al. A 2048×60m4 SRAM Design in Intel 4 With Around-the-Array Power Delivery Scheme Using PowerVia. IEEE Solid-State Circuits Letters, 2024, 7: 243-246.
[7] Ilo H. A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology. 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025: 498-500.
[8] Haraguchi M. A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024: 280-282.
[9] Wang X. A 0.021μm2 High-Density SRAM in Intel-18A-RibbonFET Technology with PowerVia-Backside Power Delivery. 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025: 494-496.
[10] Yeo M. Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node. 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024: 282-284.
[11] Fujiwara H. A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme. 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025: 500-502.
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Copyright (c) 2026 Academic Journal of Science and Technology
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