Design and Feasibility Analysis of a UART Core Based on the AES Algorithm

Yuzhi Huang

doi:10.54097/3eedxf50

Authors

Yuzhi Huang

DOI:

https://doi.org/10.54097/3eedxf50

Keywords:

UART; AES algorithm; serial communication; data security; hardware description language.

Abstract

This paper designs a Universal Asynchronous Receiver/Transmitter (UART) core integrated with an Advanced Encryption Standard (AES) algorithm encryption module, aiming to enhance the security of serial communication. By adopting the AES symmetric encryption algorithm, the UART core serves as the fundamental communication module, responsible for serializing and parallelizing data, while the encryption module performs operations such as XOR and byte substitution based on the principles of the AES algorithm. These modules not only ensure that the data is not distorted but also improve data security during transmission. With these measures, the system achieves real-time encryption and decryption of transmitted data. Then, this system successfully completes the entire process from plain-text data input and encrypted data transmission, after which it comes to reception and decryption through testbench verification. The test results demonstrate that the system can effectively improve the security of serial communication and hold broad potential and space for development in embedded systems.

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