Effects of Different Processes and Structures on CMOS Device Characteristics

Peidong Guo

doi:10.54097/h8zgbs44

Authors

Peidong Guo

DOI:

https://doi.org/10.54097/h8zgbs44

Keywords:

Complementary bipolar technology, BiCMOS technology, FinFET.

Abstract

CMOS technology is the basis of integrated circuit technology, and the characteristics of CMOS technology affect the function of the circuit. If the MOSFETs that compose the CMOS circuit use the voltage-current characteristic to amplify the signal in the “saturation region”, if they use the “variable resistance region” to work just like a variable resistor, or if they use the characteristic of threshold voltage as a voltage reference chip. These characteristics fundamentally depend on the manufacturing process employed. This paper reviews the research progress in silicon-based integrated circuit manufacturing process technology. The analysis covers the key characteristics of mainstream complementary bipolar technology, BiCMOS technology, and non-planar structure processes in the industry, along with their impact on CMOS device properties, including feature frequency. This paper aims to investigate the impact of different manufacturing processes on the development of CMOS devices, analyzing their specific effects on device characteristics and the underlying reasons.

Downloads

Download data is not yet available.

References

[1] DOBKIN B. The Evolution of Analog Circuits [J]. Electronics World, 121 (1953): 22 - 26.

[2] Fu, X. Research Progress in Analog Integrated Circuit Process Technology [J]. Microelectronics, 2024, 54 (04): 523 - 541.

[3] Zhang, X. Development and Simulation Design of Complementary Bipolar Integrated Circuit (CBIC) Process Platform [D]. Beijing University of Technology, 2016.

[4] Ou Hongqi, Liu Luncai, Hu Mingyu, et al. A PN-Junction Isolated Complementary Bipolar Process [J]. Microelectronics, 2007, (04): 548 - 552.

[5] Baccarani G, Wordeman M, Dennard R. Generalized scaling theory and its application to a ¼ micrometer MOSFET design [J]. IEEE Transactions on Electron Devices, 1984, 31 (4): 452 - 462.

[6] Xie Zhengwang, Li Rongqiang, Liu Yong, et al. A Low Dropout Regulator Based on 2μm Complementary Bipolar CMOS Process [J]. Microelectronics, 2007, (02): 274 - 278.

[7] Ma Yu, Wang Zhikuan, Cui Wei. Current Status and Development Trends of SiGe Integrated Circuit Process Technology [J]. Microelectronics, 2018, 48 (04): 508 - 514.

[8] Qi Qian. Research and Design of a 14-Bit 4 GS/s Digital-to-Analog Converter Based on SiGe HBT Technology [D]. Nanjing University of Posts and Telecommunications, 2023.

[9] Ma Yu, Zhang Peijian, Xu Xueliang, et al. Research Progress on Next-Generation Ultra-High-Speed SiGe BiCMOS Processes [J]. Microelectronics, 2023, 53 (02): 272 - 285.

[10] Guan Yulong, Chang Xiaoyang, Wang Xinhé. Historical Development of Germanium-Silicon Heterojunction Bipolar Transistors and Their Applications in High-Temperature Electronics [J]. Integrated Circuits and Embedded Systems, 2025, 25 (05): 8 - 15.

[11] Zhao Zhengping. Research Progress in Nanotechnology for FinFET/GAAFET/CFET [J]. Electronics and Packaging, 2024, 24 (08): 80 - 101.

[12] Bai Gang, Chen Cheng. Theoretical Derivation of a Physical Analytical Model for Short-Channel Negative-Capacitance GAAFETs [J]. University Physics, 2024, 43 (04): 36 - 39+55.

[13] Liu Haiyu. Research on Electrical Characteristics and Single-Particle Effects of FinFET Devices and Cell Circuits Based on Deep Learning [D]. Xi'an University of Electronic Science and Technology, 2024.

[14] Wei Chao. Research on NWaFET Inverted-Bipolar Transistor Structure and SPICE Model [D]. University of Electronic Science and Technology of China, 2025. DOI: 10.27005/d.cnki.gdzku.2025.002411.

[15] Huang X, Lee W, Kuo C, et al. Sub-50 nm P-channel FinFET [J]. IEEE Transactions on Electron Devices, 2001, 48 (5): 880 - 886.

[16] Song Peilin. Research on CMOS Device Manufacturing Processes for NWaFET Structures and Their Gate Self-Alignment Implementation Methods [D]. Electronic Science and Technology, 2025.