The Progress of Integrated Circuit Routing Optimization Driven by Artificial Intelligence

Abstract

As integrated circuit processes move towards nodes below 7nm, the latency of interconnection lines gradually surpasses that of transistors, becoming the core bottleneck restricting the improvement of chip performance. Traditional cabling tools have problems such as large estimation deviations of parasitic parameters, insufficient coordination between layout and cabling, and poor adaptability to special scenarios, which are difficult to meet the requirements of high-density integration. For this reason, artificial intelligence technology has become the key path for wiring optimization. Supervised learning, through incremental parasitic extraction technology, controls parasitic errors within 1%, helping to reduce the delay of 7nm ring oscillators by 10.79% and optimize the efficiency of quantum circuit routing. Reinforcement learning for the collaborative optimization of layout and routing has increased the routing connectivity rate by 8% and shortened the line length by 22%. Meanwhile, the problem of global routing edge overflow is solved through deep reinforcement learning. The heuristic algorithm is adapted to scenarios such as thermal sensitivity of optical networks and dynamic topology of wireless Mesh, achieving a 31.6% reduction in optical power loss and a wireless client connectivity rate of 98%. Experiments have verified the scene advantages of different AI methods, but they still face challenges such as difficult generalization with small samples and complex multi-objective balance at present. In the future, through technologies such as multimodal fusion and generative AI, AI will drive the transformation of integrated circuit design from experience-driven to data-driven precision.