Systematic Analysis of FPGA-Based Acceleration for Deep Neural Networks

Mingyang Xu

doi:10.54097/yqf8gq04

Authors

Mingyang Xu

DOI:

https://doi.org/10.54097/yqf8gq04

Keywords:

FPGA, AI acceleration, Deep Neural Networks, low latency.

Abstract

This paper systematically reviews and evaluates the architectural characteristics, application status, and platform comparisons of FPGAs for deep neural network (DNN) acceleration. First, this paper outlines the foundation of Field-Programmable Gate Array-based (FPGA-based) reconfigurable hardware based on dataflow and parallelism. Subsequently, by combining representative designs and case studies, this paper summarizes FPGA advantages in low latency, energy efficiency, and operator customization, as well as bottlenecks. Compared to Graphics Processing Units (GPUs)/ Tensor Processing Units (TPUs), which are more suitable for large-scale training and high-throughput inference, FPGAs offer cost-effectiveness in deterministic low latency, small-batch/real-time scenarios, and specific protocol/operation customization, making them suitable for cloud-edge collaboration and industrial embedded applications. Looking ahead, technologies such as High Bandwidth Memory (HBM) and hierarchical caching, near-memory/near-computing, tensor- and dataflow-based reconfiguration coverage, model hardware co-optimization based on quantization and sparsity, automated compilation, heterogeneous Central Processing Unit (CPU)/ Artificial Intelligence (AI) engine/ FPGA System on Chips (SoCs), and chiplet/3-Dimension (3D) packaging will further lower the design barrier and improve system efficiency. This article aims to provide a reference for selecting heterogeneous computing capabilities and designing FPGA accelerators in different scenarios.

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