Design of Capacitor-Less Low-Dropout (LDO) Voltage Regulator

Abstract

With the rapid proliferation of portable electronic devices and growing demands for energy efficiency, the critical role of low-dropout linear regulators (LDOs) in power management has become increasingly evident. This paper focuses on the design of capacitor-less LDO integrated circuits, providing a comprehensive and systematic analysis of existing solutions. The fundamental operating principle of LDO regulators is introduced, followed by a review of the technological evolution and development background of key research topics such as capacitor-free LDOs, high power supply rejection ratio (PSRR) LDOs, and fully integrated on-chip LDOs. To overcome the limitations of conventional capacitor-less approaches—including poor transient response, limited loop stability, and high power consumption—two mainstream design architectures for capacitor-less LDOs are analyzed in depth. The core innovations, resolved technical challenges, and resulting performance advantages of each scheme are elucidated. Furthermore, limitations and drawbacks of these designs in critical aspects such as noise susceptibility, structural complexity, and power transistor performance are critically assessed. Finally, based on the identified shortcomings, prospective optimization directions and potential technological pathways for future capacitor-less LDO designs are proposed.