FPGA-based Keyword Spotting Accelerator with Data Reuse Optimization

Abstract

Keyword Spotting (KWS), also known as wake-word detection, has become a basic component of voice systems such as smart speakers, mobile assistants and Internet of Things devices. It enables the device to continuously listen to specific commands while maintaining minimum energy consumption. With the development of neural networks, how to achieve efficient reasoning in a resource-limited environment is still a major challenge. Field Programmable Gate Array (FPGA) - a reconfigurable logic device that allows customization to be manufactured after production - provides a good balance between flexibility, power consumption and performance. This paper proposes an FPGA-based KWS accelerator optimization framework, which uses the data reuse mechanism to improve computing efficiency and reduce off-chip memory access. The system integrates the convolutional layer, activation layer and fully connected (FC) layer under a unified finite state control logic, and is modeled and simulated in Vivado 2017. The proposed row buffer-based reuse scheme minimizes redundant memory operations. Compared with the baseline design, the number of memory reads is reduced by 88.9% and the latency is reduced by 50%. The research results show that memory-centered architecture optimization can improve the reasoning performance of FPGA-based micro-machine learning (TinyML). This work provides a scalable and energy-saving framework for future intelligent edge systems.