FPGA-Based Deep Learning Acceleration: Analysis of Dataflow and Tiling Strategies

Xingke Wang

doi:10.54097/41gx1442

Authors

Xingke Wang

DOI:

https://doi.org/10.54097/41gx1442

Keywords:

Performance Optimization; FPGA Accelerators; Tiling Strategies; CNNs.

Abstract

With the fast development of deep learning models, especially Convolutional Neural Networks (CNNs) and Large Language Models (LLMs), Central Processing Units (CPUs) and Graphics Processing Units (GPUs) struggle to meet the high-performance and low-power requirements for deep learning acceleration. As a kind of reconfigurable hardware, Field-Programmable Gate Arrays (FPGAs) have exhibited great potentials for deep learning acceleration because of its efficient parallel computing and flexible nature. This paper is on the design and optimization strategies for FPGA based Deep Learning (DL) accelerators, specifically dataflow and tiling strategies. FPGA accelerators applied to deep learning architecture such as CNNs or Transformers; also consider the effects of different data flow strategy on the performance. This paper also presents ongoing bottlenecks like memory bandwidth, computational resource allocation and maturity of toolchain and future research directions like dynamic data flow, partial reconfiguration and heterogeneous computing platform integration. Lastly, this paper give an outlook for the future prospects of FPGAs in deep learning acceleration and offer some suggestions for further optimization.

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