Principal and performance analysis of three typical comparators
DOI:
https://doi.org/10.54097/hset.v27i.3721Keywords:
Comparator topology, self-calibrating technique, comparator with regeneration operating midwayAbstract
This paper discussed 3 innovative comparator topologies proposed in last several years. Depends on the target applications, each of the 3 designs achieved significant performance gains. Compared with conventional design, the comparator with self-calibrating technique has low offset voltage, small die area, low noise, and low power consumption. The comparator with regeneration operating midway realizes dramatically low operation delay with acceptable power consumption. The comparator with latch structure on amplifier stage implements circuit with high speed under low supplied voltage.
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