Analysis and comparison of several types of low-power, low offset comparators
DOI:
https://doi.org/10.54097/hset.v27i.3728Keywords:
Dynamic bias comparator, Low-Noise Self-Calibrating Dynamic comparator, Edge-Pursuit Comparator, Energy optimization, Low-offset feature.Abstract
This paper studies several excellent works of comparator constructions of comparators and compares them with the Double-tail latch-type comparator. Based on the Elzakker comparator, the comparator with a dynamic bias reduced the use of energy by partly discharging the preamplifier's output nodes. Edge-Pursuit Comparator(EPC) demonstrates a new approach to reducing energy consumption by automatic energy optimization. Apart from the designs that optimize energy consumption. Low-Noise Self-Calibrating Dynamic Comparator provides the low-offset feature while in relatively low power consumption.
Downloads
References
Razavi B, et al. The StrongARM latch [A circuit for all seasons] [M], IEEE Solid-State Circuits Mag, vol. 7, no. 2, pp. 12–17, Spring 2015.
Lam H M and Tsui C Y, et al. High-performance single clock cycle CMOS comparator [J], Electron. Lett, vol. 42, no. 2, pp. 75–77, Jan. 2006.
Schinkel D, Mensink E, Klumperink E, Ed Van Tuijl, Nauta B, et al. A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup-Hold Time [J], ISSCC Dig. of Tech. Papers, pp.314-315, Feb 2007.
Bindra H S, Lokin C E, Annema A J, and Nauta B, et al. A 30fJ/comparison dynamic bias comparator [C], in Proc. 43rd IEEE Eur. Solid State Circuits Conf. (ESSCIRC), Sep. 2017, pp. 71–74.
Shilpi Singh, et al. A novel CMOS dynamic latch comparator for low power and high speed [J], International Journal of Microelectronics Engineering (IJME), Vol. 1, No.1, 2015.
Huang C H and Wang J S, et al. High-performance and power-effificient CMOS comparators [J], IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 254– 262, Feb. 2003
Yang K, Blaauw D, Dong Q, and Sylvester D, et al. A physical unclonable function with BER <10−8 for robust chip authentication using oscillator collapse in 40nm CMOS [C], in Proc. IEEE Int.Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2015, pp. 254–255.
Shim M, et al. An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC [J], in Proc. VLSI Circuits Symp. Dig. Tech. Papers, Jun. 2016, pp. 158–159.
Coussy P and Morawiec A, et al. High-Level Synthesis: From Algorithm to Digital Circuit [J]. New York: Springer-Verlag, 2008.
Shim M, et al. An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC [J], in Proc. VLSI Circuits Symp. Dig. Tech. Papers, Jun. 2016, pp. 158–159.
Downloads
Published
Issue
Section
License

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.







