Prediction of Electric Load Neural Network Prediction Model for Big Data
DOI:
https://doi.org/10.54097/hset.v27i.3799Keywords:
Absolute-value Detector, CMOS, Optimal Energy-delay Model.Abstract
Spike sorting algorithms is a considerable significant way to collect neural signals in neural signal acquisition systems. One method to realize this function in hardware aspect is to use absolute-value detector. In this paper, the common circuit topology is given by using static CMOS and PTL technology. Then, through comparing with the delay and energy of unit reference inverter, the optimal energy-delay model when sacrificing extra 50% delay can be obtained by the way changing the size of CMOS and Vdd simultaneously, which save nearly 83% energy dissipate than minimal delay model.
Downloads
References
Gibson Sarah,Judy Jack W,Markovic Dejan. Comparison of spike-sorting algorithms for future hardware implementation. [J]. Conference proceedings: ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference,2008.
I.Obeid and P. D. Wolf, “Evaluation of spike-detection algorithms for a brain-machine interface application,” IEEE Trans. Biomed. Eng., vol. 51, no. 6, pp. 905–911, Jun. 2004.
M. Kumngern, "Absolute Value Circuit for Biological Signal Processing Applications," 2013 4th International Conference on Intelligent Systems, Modelling and Simulation, 2013, pp. 601-604, doi: 10.1109/ISMS.2013.135.
A. Zviagintsev, Y. Perelman, and R. Ginosar, “Low-power architectures for spike sorting,” in 2nd Int. IEEE EMBS Conf. Neural Eng.,Arlington, VA, Mar. 2005, pp. 162–165.
Kaveh Shakeri and James D. Meindl. A Compact Delay Model for Series-Connected MOSFETs. Proceedings of the 12th ACM Great Lakes symposium on VLSI, P37-40,2002.
Maheshwari S., Raghav H.S., Gupta A. Characterization of Logical Effort for Improved Delay.VLSI D-esign and Test. Communications in Computer and Information Science, vol 382, P108-117,2013.
Jingyue Xue, D. Al-Khalili and C. N. Rozon, "A normalized intrinsic delay model of static CMOS complex gates for deep submicron technologies," The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004., 2004, pp. 17-20
T. Sakurai.CMOS inverter delay and other formulas using alpha -power law MOS model. IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers,n.d,1988.
A. Kabbani, D. Al-Khalili and A. J. Al-Khalili, "Delay analysis of CMOS gates using modified logical effort model," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 937-947, June 2005, doi: 10.1109/TCAD.2005.847892.
A. Ma, Y. Zheng and H. Zhou, "Research on A 16.01 FO4(1V), 26.49 Eu(1V) 4-bit Absolute-Value Detector Based on CMOS transistor," 2021 International Conference on Electronic Information Engineering and Computer Science (EIECS), 2021, pp. 976-980, doi: 10.1109/EIECS53707.2021.9587975.
X. Lin, Y. Wang, S. Nazarian and M. Pedram, "An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes," Fifteenth International Symposium on Quality Electronic Design, 2014, pp. 249-256.
Downloads
Published
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
