Implementation of Rate-Compatible QC-LDPC Encoder Based on FPGA

Abstract

A rate-compatible LDPC encoder based on quasi-cyclic generation matrix is proposed. The encoder partitions and controls access to the ROM address, so it can be compatible with a variety of LDPC codes to generate matrix cyclic shift vectors. By adding routing options in the register cyclic shift circuit, it is compatible with matrix blocks of different sizes. Due to the adjustment of the initial shift count and the truncation of the check bit output, the virtual filling and shortening of the LDPC code is realized, which further expands the code length and code rate of the encoder. An LDPC encoder compatible with 4 code rates is implemented on a Xilinx Virtex5 xc5vfx130t FPGA, Compared with the existing design, this encoder requires only slightly more hardware resources than a single encoder to achieve the same data throughput. Compared with implementing all four different encoders, more than 40% of the hardware resources can be saved.