A Review of Design of Digital Clock Based on Verilog HDL
DOI:
https://doi.org/10.54097/hset.v46i.7716Keywords:
Verilog HDL, digital clock, frequency division module, counter module, decode display module, clock simulation.Abstract
With the development of electronic technology, digital clocks have added many functions that facilitate people's lives, Digital electronic clock is a device that uses digital circuits to realize the digital display of time, minutes, and seconds. This paper mainly discusses how to use Verilog HDL to design a simple digital clock and realize the basic functions such as timing and display in the clock, as well as the platform and tools used. The circuit of the digital clock is divided into three modules, namely the frequency division module, counting module, and decoding display module. And the timing process is through the LED display, and the digital tube displays "hours", "minutes", and "seconds" which are displayed in two digits. The frequency division module divides a 50 MHz input signal to obtain a 1 Hz clock signal, and the counting time module can count and adjust the time of the clock, minutes, and seconds, and then display it on the FPGA development board through the decoding display module. After clock simulation, the system realizes the function of the digital clock and meets the design requirements.
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