Acceleration Of Chip Verification Process and Defect Prediction Based on Artificial Intelligence

Yizhe Lu

doi:10.54097/eqevth05

Authors

Yizhe Lu School of Electronic Engineering, Xi'an University of Posts & Telecommunications, Xi'an, 710000, China

DOI:

https://doi.org/10.54097/eqevth05

Keywords:

Chip verification; Artificial intelligence; Process-related defects; multi-source data fusion; simulation cycle optimization.

Abstract

With the popularization of advanced manufacturing processes (3nm/2nm) and heterogeneous integration technologies, chip verification is facing challenges such as sensitivity to process deviations, complex physical effects, and a sharp increase in data volume. Traditional verification methods based on experience, such as test case writing and full-chip simulation, are inefficient and prone to missed detections. This article systematically reviews the application of artificial intelligence technology in accelerating the chip verification process and predicting defects. This paper focuses on analyzing how AI can address issues such as missed detections of process-related defects in microelectronics verification, bottlenecks in physical effect simulation, and multi-source data fusion of design parameters, process data, and test results. By combining accessible tools and open-source datasets in the microelectronics field, it explores the feasibility of technology implementation. Research shows that AI can increase the accuracy of predicting process-related defects to over 85% and shorten the simulation cycle by 40%. Future research can enhance interpretability and maintain the ability of efficient reasoning from the hybrid model that integrates symbolic reasoning and neural networks. Meanwhile, the collaborative mechanism of cross-scale verification tasks and the lightweight deployment of AI will become the key technical paths to promote the intelligence of EDA tools and the development of the open-source chip ecosystem.

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