Consumption Analysis and Optimization Strategies for Four-Bit Absolute-Value Detectors
DOI:
https://doi.org/10.54097/hset.v71i.13047Keywords:
Four-Bit Absolute-Value Detector, Digital circuits, Energy Consumption, Energy OptimizationAbstract
As embedded systems, communication systems, and neurology research continue to advance, the demand for high-performance components in digital circuits has risen. Simultaneously, there is a growing need for low-energy consumption. In this paper, Four-Bit Absolute-Value Detectors, as crucial components in digital circuits, have garnered significant attention for their role in achieving energy efficiency. This paper embarks on a comprehensive exploration, commencing with the fundamentals of circuit theory, circuit topologies, and circuit styles. Through extensive calculations and comparative studies, this paper conduct a thorough analysis of the factors influencing energy consumption in these circuits. The study reveals that various parameters have a substantial impact on energy consumption. To mitigate this, the author proposes multiple strategies, including gate size optimization, supply voltage optimization, and the selection of appropriate circuit styles. The significance of this study lies in providing foundational insights into the energy optimization of Four-Bit Absolute-Value Detectors. By investigating the interplay between gate sizes, supply voltage, path length, capacitance load, and circuit topology, this paper offer a holistic perspective on energy-efficient design.
Downloads
References
Seo J, Jin H, Yi D, et al. Two-Stage ML Detector Using Absolute Value of IQ Components and SVM for Adaptive OFDM-IM. IEEE Access, 2022, 10: 133196-133205.
Bohr M T, Young I A. CMOS scaling trends and beyond. IEEE Micro, 2017, 37(6): 20-29.
Uyemura J P. Circuit design for CMOS VLSI. Springer Science & Business Media, 2012.
Oklobdzija V G, Zeydel B R, Dao H Q, et al. Comparison of high-performance VLSI adders in the energy-delay space. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(6): 754-758.
Iranmanesh S, Raikos G, Jiang Z, et al. CMOS implementation of a low power absolute value comparator circuit. 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS). IEEE, 2016: 1-4.
Chandrakasan A P, Sheng S, Brodersen R W. Low-power CMOS digital design. IEICE Transactions on Electronics, 1992, 75(4): 371-382.
Agrawal V D, Bushnell M L, Parthasarathy G, et al. Digital circuit design for minimum transient energy and a linear programming method. Proceedings Twelfth International Conference on VLSI Design. (Cat. No. PR00013). IEEE, 1999: 434-439.
Wiltgen A, Escobar K A, Reis A I, et al. Power consumption analysis in static CMOS gates. 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI). IEEE, 2013: 1-6.
Pénzes P I, Martin A J. Energy-delay efficiency of VLSI computations. Proceedings of the 12th ACM Great Lakes symposium on VLSI. 2002: 104-111.
Chandrakasan A P, Brodersen R W. Minimizing power consumption in digital CMOS circuits. Proceedings of the IEEE, 1995, 83(4): 498-523.
Iranmanesh S, Raikos G, Jiang Z, et al. CMOS implementation of a low power absolute value comparator circuit. 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS). IEEE, 2016: 1-4.
Anacan R M, Bagay J L. Logical Effort Analysis of various VLSI design algorithms. 2015 IEEE International Conference on Control System, Computing and Engineering (ICCSCE). IEEE, 2015: 19-23.
Weste N H E, Eshraghian K. Principles of CMOS VLSI design: a systems perspective. Addison-Wesley Longman Publishing Co., Inc., 1985.
Downloads
Published
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
