Principle and performance analysis of low-power, high-speed, low-noise comparators
DOI:
https://doi.org/10.54097/hset.v27i.3724Keywords:
Comparator, Double-tailed latch-type comparator, Strong-arm latch comparator, dynamic bias, common-mode rejection, high speed, energy efficient, low noise.Abstract
This paper studies three different structures proposed in recent years and discusses their advantages and properties respectively. A modified strong-arm latch voltage comparator is adapted to 3GHz operating frequency through additional current paths in the pre-amplifier. A latch-type comparator with a dynamic-biased pre-amplifier (DA) greatly reduces energy and improves noise performance through the stabilization of the input common-mode voltage. An FIA comparator further reduces energy and noise and greatly enhances the delay performance and the robustness of the comparator against different input common-mode voltage.
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Siddharth R, Satyanarayana Y, Nithin Kumar Y, Vasantha M and Bonizzoni E. A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 12, pp. 2918-2922, Dec. 2020.
Bindra H, Lokin C, Schinkel D, Annema A and Nauta B. A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise [J]. IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 1902-1912, July 2018.
Tang X. et al. An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier [J]. IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1011-1022, April 2020.
Figueiredo P and Vital J. Kickback noise reduction techniques for CMOS latched comparators [J]. IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp. 541-545, July 2006.
Elzakker M, Tuijl E, Geraedts P, Schinkel D, Klumperink E and Nauta B. A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s [J]. IEEE Journal of Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010.
Nuzzo P, Bernardinis F, Terreni P and Plas G. Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008.
Sepke T, Holloway P, Sodini C and Lee H. Noise Analysis for Comparator-Based Circuits [J]. IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 3, pp. 541-553, March 2009.
Akter M, Makinwa K and Bult K. A Capacitively Degenerated 100-dB Linear 20–150 MS/s Dynamic Amplifier [J]. IEEE Journal of Solid-State Circuits, vol. 53, no. 4, pp. 1115-1126, April 2018.
Tang X, Chen L, Song J and Sun N. A 10-b 750µW 200MS/s fully dynamic single-channel SAR ADC in 40nm CMOS [C]. ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 413-416.
Bindra H, Lokin C, Annema A and Nauta B. A 30fJ/comparison dynamic bias comparator [C]. ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 71-74.
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