Power Optimization in 3D NAND Flash: A Co-Design Study of Architecture, Circuits, and Algorithms

Ziqi Xie

doi:10.54097/wsxxnc64

Authors

Ziqi Xie

DOI:

https://doi.org/10.54097/wsxxnc64

Keywords:

3D NAND flash, power consumption, collaborative analysis, near-memory computing.

Abstract

As data for storage and calculation continues to explode, 3D NAND flash is a key technology for storing information because of its high density. However, adding more layers of stacks and computer functions has led to the problem of power consumption, restricting further advancement. To solve this kind of challenge, in this paper, we creatively utilized a three-layer collaborative analysis framework at the architecture, circuit, and algorithm levels. The architecture level is like near-memory computing, but it gives me a little taste of what the hardware is doing. Then, have full link EE management and exact circuit control for the circuit to cut hardware cost. In terms of algorithms. Dynamic power—optimize based on intelligent prediction and global scheduling, research and study the internal relationship and principles of promoting and supporting the optimization method at different levels of research, create more collaborative rules in fewer lines, can really decrease hardware leakage, and can also respond to changes in regulations in real time. It supplies basic theoretical aid with specific systemic directions on low energy use, extremely thick 3D NAND memory storage systems, and the associated computation combined systems.

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References

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