A New Design of A 6-Bit Absolute Value Detector by Using Both VDD Scaling and Sizing to Optimize

Abstract

The presented paper focuses on the development and optimization of a 6-bit absolute value detector, a crucial digital block in encoder and decoder applications. The primary objective is to minimize energy consumption while maintaining a delay no greater than 1.5 times the minimum delay. The optimization process combines logical effort theory with gate sizing and voltage scaling techniques. Firstly, gate sizes are adjusted while keeping VDD constant, achieving a 73% reduction in energy consumption, reaching a delay constraint of 1.5 times the minimum delay. Secondly, VDD scaling is explored without altering gate sizes, resulting in a 40% reduction in energy consumption, reaching the minimum energy consumption point. Finally, gate sizing and VDD scaling are combined, yielding a remarkable 79% reduction in total energy consumption, with a supply voltage of 0.835 volts. These optimization strategies bridge a research gap in 6-bit absolute value detectors, significantly enhancing energy efficiency and offering valuable insights for intricate digital signal processing scenarios. The findings showcase the effectiveness of combining logical effort theory with gate sizing and voltage scaling to achieve substantial energy savings while meeting stringent delay constraints.