Enhancement Of A 32-By-32-Bit Signed Digital Multiplier: A Multi-Dimensional Optimization Approach

Abstract

In the pursuit of enhanced performance in a 32-by-32-bit signed digital multiplier, optimizations were enacted on three critical fronts. Initial efforts focused on the integration of an advanced Booth encoding technique for the generation of three-bit control signals, meticulously crafted in the Verilog programming language. This approach, characterized by its restricted symbol expansion methodology, strategically curtails hardware resource expenditures, and diminishes power utilization during computational tasks. Subsequently, a sophisticated hybrid Wallace tree architecture was employed, offering a notable decrement in the delay of two XOR gates in contrast to the exclusive application of 3-2 and 4-2 compressors. This refinement not only augments the aggregation efficacy of partial products but also substantially accelerates operational velocity. Furthermore, the incorporation of a 64-bit carry-lookahead adder was instrumental in mitigating the latency induced by lower-order carry anticipation. To ascertain the multiplier's computational precision, a Verilog-constructed testbench file facilitated the assembly of 100,000 test vectors, with simulations executed in ModelSim yielding a verifiable accuracy rate of 100%.