An FPGA-Based Adaptive Solution for Synchronous Configuration in UART Communication

Abstract

To address the challenges associated with data reception failures, which arise due to abrupt alterations in the baud rate and the data format of the transmission signal in traditional Universal Asynchronous Receiver-Transmitter (UART) scenarios, this study presents an adaptive UART parameter solution underpinned by Field-Programmable Gate Array (FPGA) technology. Initially, this manuscript elucidates the underlying principles of UART communication and delineates the pivotal constituents of the UART protocol. Subsequently, it offers an in-depth analysis, from the transmission perspective, of how specific parameters influence the effectiveness of the UART protocol. Based on the software and hardware embodiments associated with the dual primary functions – baud rate adaptation and data format adaptation – this paper extensively details the flow chart for baud rate adaptation, the circuitry for edge detection, methodologies for baud rate computation, and the parameter eigenvalue approach. Following this, Verilog, a hardware description language, is employed for coding and subsequent simulation within the Quartus II environment. Empirical evidence corroborates the efficacy of the proposed design in achieving synchronous configuration between the baud rate and the data format. The findings of this research bear substantial implications for augmenting both the adaptability and dependability of UART communication systems.