Acceleration System for Single-Precision Floating-Point Arithmetic Based on IEEE754 Standard

Junxuan Yang

doi:10.54097/42rhk490

Authors

Junxuan Yang

DOI:

https://doi.org/10.54097/42rhk490

Keywords:

IEEE754 standard; adder; exponent; mantissa.

Abstract

In recent literature, there has been a heightened interest in the algorithms underpinning artificial intelligence. The crux of this research is the integration of these algorithms into embedded systems. Fundamental to these algorithms are arithmetic operations such as addition and multiplication. This study introduces an implementation of single-precision floating-point arithmetic in compliance with the IEEE754 standard. Adopting a modular approach, the system is deconstructed into distinct modules for addition, subtraction, multiplication, and division, each with its own unique implementation. Within an individual module, components such as sign, exponent, and mantissa are distinctly treated. Delving into the mathematical intricacies of the exponent and mantissa allows for the formulation of the subsequent programming. This study proposes a rounding operation to facilitate diverse rounding modes for the data. Advanced techniques such as the over-advancing adder and Zero judgement are employed to enhance the adder's speed, and constructs like Overflow and Error are introduced to evaluate the output data's status in adherence to the IEEE754 standard. Functional tests of the modules were conducted on a designated platform. A timing simulation was performed using ModelSim, corroborating the robust performance of the proposed system.

Downloads

Download data is not yet available.

References

Li Z, Liu F, Yang W, et al. A survey of convolutional neural networks: analysis, applications, and prospects. IEEE transactions on neural networks and learning systems, 2021.

Daoud L, Zydek D, Selvaraj H. A survey on design and implementation of floating-point adder in FPGA. Progress in Systems Engineering: Proceedings of the Twenty-Third International Conference on Systems Engineering. Springer International Publishing, 2015: 885-892.

Kahan W. IEEE standard 754 for binary floating-point arithmetic. Lecture Notes on the Status of IEEE, 1996, 754(94720-1776): 11.

Brain M, Tinelli C, Rümmer P, et al. An automatable formal semantics for IEEE-754 floating-point arithmetic. 2015 IEEE 22nd Symposium on Computer Arithmetic. IEEE, 2015: 160-167.

Benz F, Hildebrandt A, Hack S. A dynamic program analysis to find floating-point accuracy problems. ACM SIGPLAN Notices, 2012, 47(6): 453-462.

Wiśniewski R, Bukowiec A, Węgrzyn M. Benefits of hardware accelerated simulation. Proceedings of the International Workshop Discrete-Event System Design (DESDes), Poland. 2001: 229-234.

Louca. Implementation of IEEE single precision floating point addition and multiplication on FPGAs. 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines. IEEE, 1996: 107-116.

Nachtigal M, Thapliyal H, Ranganathan N. Design of a reversible floating-point adder architecture. 2011 11th IEEE International Conference on Nanotechnology. IEEE, 2011: 451-456.

Hasan M, Islam M S, Ahmed M R. Performance improvement of 4-bit static CMOS carry look-ahead adder using modified circuits for carry propagate and generate terms. Science Journal of Circuits, Systems and Signal Processing, 2019, 8(2): 76-81.

Kornerup P, Lefevre V, Louvet N, et al. On the computation of correctly rounded sums. IEEE Transactions on Computers, 2011, 61(3): 289-298.

Daoud L, Zydek D, Selvaraj H. A survey on design and implementation of floating-point adder in FPGA. Progress in Systems Engineering: Proceedings of the Twenty-Third International Conference on Systems Engineering. Springer International Publishing, 2015: 885-892.

Jain A, Dash B, Panda a K, et al. FPGA design of a fast 32-bit floating point multiplier unit. 2012 International Conference on Devices, Circuits and Systems (ICDCS). IEEE, 2012: 545-547.

Even G, Paul W. On the design of IEEE compliant floating-point units. Proceedings 13th IEEE Sympsoium on Computer Arithmetic. IEEE, 1997: 54-63.