A 93.56 FO4(1V), 141.36 Eu(1V) 4-bit Absolute-Value Detector

Authors

  • Qianqing Wang

DOI:

https://doi.org/10.54097/hset.v27i.3801

Keywords:

MOS, comparator, absolute, MATLAB.

Abstract

With the development of technology and The Times, the industry has higher and higher requirements for chip performance. Using better circuit design to achieve this goal has become the direction of researchers today. The 4-bit absolute value detector is one of the most important and basic circuits in computer storage and data processing. The effective improvement of its performance will greatly promote the improvement of processing efficiency in the whole chip industry. This project is to design a circuit of a 4-bit absolute value detector. The main functions it implements are it can get the absolute value of 2’s complement, then compare the 3-bit absolute value with a 3-bit threshold value. This paper first divides the design into three parts: absolute module, comparison module and other small modules. Minimize the delay by exploring the critical path and changing the gate size. Finally, through theoretical calculation and optimization, the optimal scheme designed in this paper is determined. The results of this paper will be helpful to the further development of related industries.

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References

Maheshwari S., Raghav H.S., Gupta A. Characterization of Logical Effort for Improved Delay.VLSI D-esign and Test. Communications in Computer and Information Science, vol 382, P108-117,2013.

J. Yuan, C. Svensson. High-speed CMOS circuit technique. IEEE Journal of Solid-State Circuits, Volume: 24, P62-70,1989.

Mehmet A. Chitt. TRANSISTOR SIZING IN CMOS CIRCUITS. Proceedings of the 24th ACM/IEEE, Design Automation Conference, P 121-124,1987.

T. Sakurai, A.R. Newton. Delay analysis of series-connected MOSFET circuits. IEEE Journal of Solid-State Circuits, Volume: 26, Issue: 2, P122-131,1991.

Sakurai, Takayasu and A. Richard Newton. “A simple MOSFET model for circuit analysis.” IEEE Transactions on Electron Devices 38 (1991): 887-894.

Sakurai, Takayasu and A. Richard Newton. “Delay analysis of series-connected MOSFET circuits.” IEEE Journal of Solid-state Circuits 26 (1991): 122-131.

Shur, Michael S., Tor A. Fjeldly, Trond Ytterdal and Kie Young Lee. “Unified MOSFET model.” Solid-state Electronics 35 (1992): 1795-1802.

Elzakker, M.V., Tuijl, E.V., Geraedts, P.F., Schinkel, D., Klumperink, E.A., & Nauta, B. (2010). A 10-bit Charge-Redistribution ADC Consuming 1.9 $mu$W at 1 MS/s. IEEE Journal of Solid-State Circuits, 45, 1007-1015.

Hedenstierna, N., & Jeppson, K.O. (1987). CMOS Circuit Speed and Buffer Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 6, 270-281.

T. Sakurai; A.R. Newton. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE Journal of Solid-State Circuits ,Volume: 25, Issue: 2,pages 584-594,1990.

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Published

27-12-2022

How to Cite

Wang , Q. (2022). A 93.56 FO4(1V), 141.36 Eu(1V) 4-bit Absolute-Value Detector. Highlights in Science, Engineering and Technology, 27, 457-464. https://doi.org/10.54097/hset.v27i.3801