Optimized Design of a 4-bits Absolute-Value Detector
DOI:
https://doi.org/10.54097/hset.v31i.5145Keywords:
Adder circuit, Logic Effort, Energy Optimization.Abstract
4-bits Absolute Value Detector circuit is a very commonly used circuit design. As to simplify the internal circuit design to make the total number of stage lesser which provides a less critical path circuit delay. Generally, this paper used combination of static CMOS design and the path transistor circuit design to design our circuit. After we got the optimized design, we applied the logic effort calculation to calculate the minimum delay of the circuit and determined the specific gate sizing value for each logic component. The energy optimization can be obtained by increasing our delay and adjusting the power supply (VDD) value. Eventually, we sacrifice our delay a little bit to get a huge amount of energy reduction.
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