Design And Implementation of UART Based on Verilog HDL
DOI:
https://doi.org/10.54097/hset.v38i.5981Keywords:
UART, Verilog HDL, full-duplex serial communication, Modelsim.Abstract
As a two-way transmission channel, Universal Asynchronous Receiver/Transmitter (UART) not only greatly improves the efficiency of information transmission between computers and external devices, but also ensures the accuracy and consistency of information by eliminating metastable state, setting baud rate and other means. In this paper, on the basis of fully understanding the definition and function of UART, based on Verilog HDL language to build UART, and through Modelsim simulation, image and data. The experimental results show that the receiving and sending module of this module works well and meets the requirements of full-duplex serial communication equipment. There is no doubt that the design of this paper has made a more detailed explanation of the basic operating principle of UART, which will contribute to its further development.
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