An Review of Dynamic CMOS Comparators
DOI:
https://doi.org/10.54097/hset.v44i.7273Keywords:
Comparator, Analog-to-digital converter (ADC), CMOS, latch, amplifiers, double-tail latch-type comparator, StrongARM comparator, Elzakker’s comparator, low power consumption, low-noise, high gain, high speed, dynamic biasing, three-stage, partially charge, kickback-noise.Abstract
CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.
Downloads
References
Yogesh Sachdeva, Nalin Nehra, Shikhar Bansal, and Garima. Review of dynamic comparators for adcs. In 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC), pages 83–90, 2021.
R. Sangeetha, A. Vidhyashri, M. Reena, R. B. Sudharshan, Sangeetha govindan, and J. Ajayan. An overview of dynamic cmos comparators. In 2019 5th International Conference on Advanced Computing Communication Systems (ICACCS), pages 1001–1004, 2019.
Harijot Singh Bindra, Christiaan E. Lokin, Daniel Schinkel, Anne-Johan Annema, and Bram Nauta. A 1.2-v dynamic bias latch-type comparator in 65-nm cmos with 0.4-mv input noise. IEEE Journal of Solid-State Circuits, 53(7):1902–1912, 2018.
Subhash Chevella, Daniel O’Hare, and Ivan O’Connell. A low-power 1-v supply dynamic comparator. IEEE Solid-State Circuits Letters, 3:154–157, 2020.
Behzad Razavi. The strongarm latch [a circuit for all seasons]. IEEE Solid-State Circuits Magazine, 7(2):12–17, 2015.
T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, and O. Watanabe. A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture. In 1992 Symposium on VLSI Circuits Digest of Technical Papers, pages 28–29, 1992.
Athanasios T. Ramkaj, Michiel S. J. Steyaert, and Filip Tavernier. A 13.5-gb/s 5-mv-sensitivity 26.8-ps-clk–out delay triple-latch feedforward dynamic comparator in 28-nm cmos. IEEE Solid-State Circuits Letters, 2(9):167–170, 2019.
Daniel Schinkel, Eisse Mensink, Eric Klumperink, Ed van Tuijl, and Bram Nauta. A double-tail latch-type voltage sense amplifier with 18ps setup+hold time. In 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pages 314–605, 2007.
Michiel van Elzakker, Ed van Tuijl, Paul Geraedts, Danie¨l Schinkel, Eric A. M. Klumperink, and Bram Nauta. A 10-bit charge- redistribution adc consuming 1.9 ¡formula formulatype=”inline”¿¡tex notation=”tex”¿µ¡/tex¿¡/formula¿w at 1 ms/s. IEEE Journal of Solid-State Circuits, 45(5):1007–1015, 2010.
Harijot Singh Bindra, Chris E. Lokin, Anne-Johan Annema, and Bram Nauta. A 30fj/comparison dynamic bias comparator. In ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, pages 71–74, 2017.
Downloads
Published
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
How to Cite
