A Way to Optimize Delay of Carry-Skip Adders by Using Blocks of Variable Sizes

Abstract

As one of the most common operational modules in computer processors, the optimization of the propagation delay of adders has attracted extensive attention of researchers. This article proposes a method of optimizing the delay of carry-skip adders by using blocks of variable sizes. By increasing the sizes of the bypass stages gradually and then decreasing it stage by stage, keeping the delay of the first and last stage short, the total propagation delay is optimized. Compared with fixed size carry-skip adders, the delay of variable sizes carry-skip adders has a square root relationship with the number of bits. Thus, when the number of bits is large, the propagation delay is significantly reduced. After calculation, when the number of bits is 16, the propagation delay decreases by 16.67%, and when the number of bits is 256, it decreases by 52.78%. Due to the shorter propagation delay, variable sizes carry-skip adders have faster operation speed and can be applied to improve the performance of computer processors.