A Novel Design Method for 4-bit Absolute-Value Detector
DOI:
https://doi.org/10.54097/hset.v27i.3783Keywords:
Comparator, Detector, Path-effort.Abstract
The wide use of comparator reinforces its improvements and innovations. For seeking a breakthrough, a 4-Bit Absolute-value Detector is studied and constructed. Different from common designs, this new version adds an absolute value converter using truth table. Owing to the participation of absolute value detector the comparator can compare the absolute value of the two inputs' value directly in this detector. Furthermore, the detector’s delay and energy consumption which are calculated by critical path data demonstrates the performance of the detector and provides circuit optimization scheme indirectly. The analysis indicates that this improved version's minimum and maximum delay is 50.556 and 75.834 and energy consumption is 39.8% lower when supplied by optimal VDD than 1V VDD. Combining the converter with the comparator, a 4-Bit Absolute-value Detector model with smaller size and higher efficiency is built.
Downloads
References
Fei Yu, Lei Gao, Lixiang Li, Ke Gu, Weizheng Wang, and Shuo Cai. A survey on the design of current comparator[C]. In 2019 IEEE 2nd Interna-tional Conference on Electronic Information and Communication Technology (ICEICT), 2019, p:426–431.
Roohollah Sanati, Farzan Khatib, Mohammad Javadian Sarraf, and Rei-haneh Kardehi Moghaddam. Low-power bulk-driven time-domain comparator with high voltage-to-time gain for ADC applications[J]. Microelectron-ics Journal, 2022,128:105555.
Xinhang Dong, Boyuan Jing, and Xiang Yang. Improved design of a 4-bit absolute-value detector using simplified chain carry adder[J]. In Journal of Physics: Conference Series, 2021, 2113:12043
Soolmaz Abbasalizadeh, Behjat Forouzandeh, and Hossein Aghababa. 4 bits comparator design based on reversible logic gates[D]. Lecture Notes on Information Theory, 2013,1(3).
David T. Wang. An algorithm for the generation of test sets for combinational logic networks[J]. IEEE Transactions on Computers, 1975, 100(7):742–746.
Habib Youssef, Eugene Shragowitz, and Lionel Bening. Critical path issue in vlsi design. In 1989 IEEE International Conference on Computer-Aided Design, 1989, p:520–521.
Mile K Stojcev. Neil He Weste, David Harris: CMOS VSLI design: A circuits and systems perspectives[D]. Addison Wesley, Electronics and Energetics, 2004, 17(3):467–469.
Ivan E Sutherland and Robert F Sproull. Logical effort: Designing for speed on the back of an envelope[D], 1991.
Vladimir Stojanovic, Dejan Markovic, Borivoje Nikolic, Mark A Horowitz, and Robert W Brodersen. Energy-delay trade-offs in combinational logic using gate sizing and supply voltage optimization[C]. In Proceedings of the 28th European Solid-State Circuits Conference, 2002, p:211–214.
Dao H.Q, Zeydel B.R, and Oklobdzija V.G. Energy minimization method for optimal energy-delay extraction[C]. In ESSCIRC 2004 - 29th European Solid-State Circuits Conference, 2003, p:177–180.
Downloads
Published
Issue
Section
License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
How to Cite
